1/*
2 * Copyright (c) 2017 Google LLC.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <mem.h>
8#include <arm/armv6-m.dtsi>
9#include <zephyr/dt-bindings/adc/adc.h>
10#include <zephyr/dt-bindings/gpio/gpio.h>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/pwm/pwm.h>
13
14/ {
15	aliases {
16		adc-0 = &adc;
17
18		port-a = &porta;
19		port-b = &portb;
20
21		sercom-0 = &sercom0;
22		sercom-1 = &sercom1;
23		sercom-2 = &sercom2;
24		sercom-3 = &sercom3;
25		sercom-4 = &sercom4;
26		sercom-5 = &sercom5;
27
28		tc-4 = &tc4;
29
30		watchdog0 = &wdog;
31	};
32
33	chosen {
34		zephyr,flash-controller = &nvmctrl;
35	};
36
37	cpus {
38		#address-cells = <1>;
39		#size-cells = <0>;
40
41		cpu0: cpu@0 {
42			compatible = "arm,cortex-m0+";
43			reg = <0>;
44
45			device_type = "cpu";
46		};
47	};
48
49	sram0: memory@20000000 {
50		compatible = "mmio-sram";
51	};
52
53	id: device_id@80a00c {
54		compatible = "atmel,sam0-id";
55		reg =	<0x0080A00C 0x4>,
56			<0x0080A040 0x4>,
57			<0x0080A044 0x4>,
58			<0x0080A048 0x4>;
59	};
60
61	soc {
62		nvmctrl: nvmctrl@41004000  {
63			compatible = "atmel,sam0-nvmctrl";
64			reg = <0x41004000 0x22>;
65			interrupts = <5 0>;
66
67			#address-cells = <1>;
68			#size-cells = <1>;
69
70			lock-regions = <16>;
71
72			flash0: flash@0 {
73				compatible = "soc-nv-flash";
74
75				write-block-size = <4>;
76			};
77		};
78
79		pm: pm@40000400 {
80			compatible = "atmel,samd2x-pm";
81			reg = <0x40000400 0x400>;
82			interrupts = <0 0>;
83
84			#clock-cells = <2>;
85		};
86
87		gclk: gclk@40000c00 {
88			compatible = "atmel,samd2x-gclk";
89			reg = <0x40000c00 0x400>;
90
91			#clock-cells = <1>;
92		};
93
94		eic: eic@40001800 {
95			compatible = "atmel,sam0-eic";
96			reg = <0x40001800 0x1C>;
97			interrupts = <4 0>;
98		};
99
100		pinmux_a: pinmux@41004400 {
101			compatible = "atmel,sam0-pinmux";
102			reg = <0x41004400 0x80>;
103		};
104
105		pinmux_b: pinmux@41004480 {
106			compatible = "atmel,sam0-pinmux";
107			reg = <0x41004480 0x80>;
108		};
109
110		wdog: watchdog@40001000 {
111			compatible = "atmel,sam0-watchdog";
112			reg = <0x40001000 9>;
113			interrupts = <2 0>;
114		};
115
116		sercom0: sercom@42000800 {
117			compatible = "atmel,sam0-sercom";
118			reg = <0x42000800 0x40>;
119			status = "disabled";
120		};
121
122		sercom1: sercom@42000c00 {
123			compatible = "atmel,sam0-sercom";
124			reg = <0x42000c00 0x40>;
125			status = "disabled";
126		};
127
128		sercom2: sercom@42001000 {
129			compatible = "atmel,sam0-sercom";
130			reg = <0x42001000 0x40>;
131			status = "disabled";
132		};
133
134		sercom3: sercom@42001400 {
135			compatible = "atmel,sam0-sercom";
136			reg = <0x42001400 0x40>;
137			status = "disabled";
138		};
139
140		sercom4: sercom@42001800 {
141			compatible = "atmel,sam0-sercom";
142			reg = <0x42001800 0x40>;
143			status = "disabled";
144		};
145
146		sercom5: sercom@42001c00 {
147			compatible = "atmel,sam0-sercom";
148			reg = <0x42001c00 0x40>;
149			status = "disabled";
150		};
151
152		tc4: tc@42003000 {
153			compatible = "atmel,sam0-tc32";
154			reg = <0x42003000 0x20>;
155			status = "disabled";
156		};
157
158		pinctrl: pinctrl@41004400 {
159			compatible = "atmel,sam0-pinctrl";
160			ranges = <0x41004400 0x41004400 0x100>;
161
162			#address-cells = <1>;
163			#size-cells = <1>;
164
165			porta: gpio@41004400 {
166				compatible = "atmel,sam0-gpio";
167				reg = <0x41004400 0x80>;
168
169				#atmel,pin-cells = <2>;
170				#gpio-cells = <2>;
171
172				gpio-controller;
173			};
174
175			portb: gpio@41004480 {
176				compatible = "atmel,sam0-gpio";
177				reg = <0x41004480 0x80>;
178
179				#atmel,pin-cells = <2>;
180				#gpio-cells = <2>;
181
182				gpio-controller;
183			};
184		};
185
186		rtc: rtc@40001400 {
187			compatible = "atmel,sam0-rtc";
188			reg = <0x40001400 0x1C>;
189			interrupts = <3 0>;
190			status = "disabled";
191
192			clock-generator = <0>;
193		};
194
195		adc: adc@42004000 {
196			compatible = "atmel,sam0-adc";
197			reg = <0x42004000 0x2B>;
198			status = "disabled";
199
200			#io-channel-cells = <1>;
201
202			/*
203			 * 2.1 MHz max, so clock it with the
204			 * 8 MHz GCLK / 4 = 2 MHz
205			 */
206			gclk = <3>;
207			prescaler = <4>;
208		};
209
210		dac0: dac@42004800 {
211			compatible = "atmel,sam0-dac";
212			reg = <0x42004800 0x10>;
213			status = "disabled";
214
215			#io-channel-cells = <0>;
216		};
217	};
218};
219
220&nvic {
221	arm,num-irq-priority-bits = <2>;
222};
223