| /trusted-firmware-a-latest/plat/imx/imx8m/ddr/ |
| D | lpddr4_dvfs.c | 37 uint32_t val; in lpddr4_swffc() local
55 val = (init_fsp == 1) ? 0x2 << 6 : 0x1 << 6; in lpddr4_swffc()
56 emr3 = (emr3 & 0x003f) | val | 0x0d00; in lpddr4_swffc()
76 val = mmio_read_32(DDRC_MRSTAT(0)); in lpddr4_swffc()
77 } while (val & 0x1); in lpddr4_swffc()
84 val = mmio_read_32(DDRC_PSTAT(0)); in lpddr4_swffc()
85 } while (val != 0); in lpddr4_swffc()
93 val = mmio_read_32(DDRC_DFILPCFG0(0)); in lpddr4_swffc()
94 if (val & 0x100) { in lpddr4_swffc()
97 val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack in lpddr4_swffc()
[all …]
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| /trusted-firmware-a-latest/plat/brcm/board/stingray/src/ |
| D | paxc.c | 99 static void paxc_rc_cfg_write(uint32_t where, uint32_t val) in paxc_rc_cfg_write() argument
103 mmio_write_32(PAXC_BASE + PAXC_CFG_IND_DATA_OFFSET, val); in paxc_rc_cfg_write()
118 uint32_t val; in paxc_cfg_link_cap() local
120 val = paxc_rc_cfg_read(PAXC_CFG_LINK_CAP_OFFSET); in paxc_cfg_link_cap()
121 val &= ~(PAXC_RC_LINK_CAP_SPD_MASK | PAXC_RC_LINK_CAP_WIDTH_MASK); in paxc_cfg_link_cap()
122 val |= (PAXC_RC_LINK_CAP_SPD << PAXC_RC_LINK_CAP_SPD_SHIFT) | in paxc_cfg_link_cap()
124 paxc_rc_cfg_write(PAXC_CFG_LINK_CAP_OFFSET, val); in paxc_cfg_link_cap()
132 uint32_t val; in paxc_cfg_id() local
134 val = (PAXC_RC_VENDOR_ID << PAXC_RC_VENDOR_ID_SHIFT) | in paxc_cfg_id()
136 paxc_rc_cfg_write(PAXC_CFG_ID_OFFSET, val); in paxc_cfg_id()
[all …]
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| D | bl31_setup.c | 79 unsigned int val; in brcm_stingray_dma_pl330_init() local
93 val = (DMAC_STREAM_ID << DMAC_SID_SHIFT); in brcm_stingray_dma_pl330_init()
94 mmio_write_32(ICFG_DMAC_SID_ARADDR_CONTROL, val); in brcm_stingray_dma_pl330_init()
95 mmio_write_32(ICFG_DMAC_SID_AWADDR_CONTROL, val); in brcm_stingray_dma_pl330_init()
313 unsigned int val; in brcm_stingray_amac_init() local
318 val = SR_SID_VAL(0x3, 0x0, 0x4) << ICFG_AMAC_SID_SHIFT; in brcm_stingray_amac_init()
319 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_AWADDR_OFFSET, val); in brcm_stingray_amac_init()
320 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_ARADDR_OFFSET, val); in brcm_stingray_amac_init()
393 unsigned int val; in brcm_stingray_smmu_init() local
400 val = mmio_read_32(smmu_base + 0x0); in brcm_stingray_smmu_init()
[all …]
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| D | sdio.c | 33 unsigned int val; in brcm_stingray_sdio_init() local
41 val = SDIO0_CAP0_CFG; in brcm_stingray_sdio_init()
42 INFO("caps0 0x%x\n", val); in brcm_stingray_sdio_init()
43 mmio_write_32(sdio0_cfg->cfg_base + ICFG_SDIO_CAP0, val); in brcm_stingray_sdio_init()
46 val = SDIO0_CAP1_CFG; in brcm_stingray_sdio_init()
47 INFO("caps1 0x%x\n", val); in brcm_stingray_sdio_init()
48 mmio_write_32(sdio0_cfg->cfg_base + ICFG_SDIO_CAP1, val); in brcm_stingray_sdio_init()
61 val = SR_SID_VAL(0x3, 0x0, 0x2) << SDIO_SID_SHIFT; in brcm_stingray_sdio_init()
62 mmio_write_32(sdio0_cfg->sid_base + ICFG_SDIO_SID_ARADDR, val); in brcm_stingray_sdio_init()
63 mmio_write_32(sdio0_cfg->sid_base + ICFG_SDIO_SID_AWADDR, val); in brcm_stingray_sdio_init()
[all …]
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| D | paxb.c | 286 uint32_t val, link_speed; in paxb_rc_link_init() local
302 val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_CAP); in paxb_rc_link_init()
303 val &= ~CFG_RC_LINK_CAP_WIDTH_MASK; in paxb_rc_link_init()
304 val |= (link_width << CFG_RC_LINK_CAP_WIDTH_SHIFT); in paxb_rc_link_init()
305 paxb_rc_cfg_write(core_idx, CFG_RC_LINK_CAP, val); in paxb_rc_link_init()
308 val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_CAP); in paxb_rc_link_init()
309 val &= ~CFG_RC_LINK_CAP_SPEED_MASK; in paxb_rc_link_init()
310 val |= link_speed << CFG_RC_LINK_CAP_SPEED_SHIFT; in paxb_rc_link_init()
311 paxb_rc_cfg_write(core_idx, CFG_RC_LINK_CAP, val); in paxb_rc_link_init()
314 val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_STATUS_CTRL_2); in paxb_rc_link_init()
[all …]
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| /trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/pwm/ |
| D | pwm.c | 29 uint32_t i, val; in disable_pwms() local
34 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); in disable_pwms()
35 if (((val >> GRF_GPIO4C2_IOMUX_SHIFT) & in disable_pwms()
38 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, in disable_pwms()
40 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in disable_pwms()
43 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); in disable_pwms()
44 if (((val >> GRF_GPIO4C6_IOMUX_SHIFT) & in disable_pwms()
47 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, in disable_pwms()
49 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); in disable_pwms()
52 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX); in disable_pwms()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/drivers/smmu/ |
| D | smmu.c | 32 uint32_t val, cb_idx, smmu_id, ctx_base; in tegra_smmu_init() local
37 val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); in tegra_smmu_init()
38 val |= SMMU_GSR0_PGSIZE_64K; in tegra_smmu_init()
39 val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; in tegra_smmu_init()
40 tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); in tegra_smmu_init()
43 val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); in tegra_smmu_init()
44 val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; in tegra_smmu_init()
45 tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); in tegra_smmu_init()
51 val = tegra_smmu_read_32(smmu_id, in tegra_smmu_init()
53 val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT; in tegra_smmu_init()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/drivers/pmc/ |
| D | pmc.c | 32 uint32_t val; in tegra_pmc_cpu_on() local
37 val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); in tegra_pmc_cpu_on()
38 if ((val & (1U << pmc_cpu_powergate_id[cpu])) == 0U) { in tegra_pmc_cpu_on()
44 val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); in tegra_pmc_cpu_on()
45 } while ((val & PMC_TOGGLE_START) != 0U); in tegra_pmc_cpu_on()
50 val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; in tegra_pmc_cpu_on()
51 tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); in tegra_pmc_cpu_on()
58 val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); in tegra_pmc_cpu_on()
59 } while ((val & (1U << 8)) != 0U); in tegra_pmc_cpu_on()
63 val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); in tegra_pmc_cpu_on()
[all …]
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| /trusted-firmware-a-latest/plat/brcm/board/stingray/driver/ext_sram_init/ |
| D | ext_sram_init.c | 181 unsigned int val, tmp; in brcm_stingray_pnor_sram_init() local
202 val = (0xfe << PNOR_ICFG_CS_x_MASK0_SHIFT); in brcm_stingray_pnor_sram_init()
203 val |= (0x74); in brcm_stingray_pnor_sram_init()
204 mmio_write_32((uintptr_t)(PNOR_ICFG_CS_0), val); in brcm_stingray_pnor_sram_init()
206 val = (0xfe << PNOR_ICFG_CS_x_MASK0_SHIFT); in brcm_stingray_pnor_sram_init()
207 val |= (0x76); in brcm_stingray_pnor_sram_init()
208 mmio_write_32((uintptr_t)(PNOR_ICFG_CS_1), val); in brcm_stingray_pnor_sram_init()
210 val = (0x00 << PNOR_ICFG_CS_x_MASK0_SHIFT); in brcm_stingray_pnor_sram_init()
211 val |= (0xff); in brcm_stingray_pnor_sram_init()
212 mmio_write_32((uintptr_t)(PNOR_ICFG_CS_2), val); in brcm_stingray_pnor_sram_init()
[all …]
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| /trusted-firmware-a-latest/drivers/nxp/gpio/ |
| D | nxp_gpio.c | 23 uint32_t val = 0U; in set_gpio_bit() local
39 val = gpio_read32(gpdir); in set_gpio_bit()
40 val = val | bit_num; in set_gpio_bit()
41 gpio_write32(gpdir, val); in set_gpio_bit()
44 val = gpio_read32(gpdat); in set_gpio_bit()
45 val = val | bit_num; in set_gpio_bit()
46 gpio_write32(gpdat, val); in set_gpio_bit()
48 val = gpio_read32(gpdat); in set_gpio_bit()
50 if ((val & bit_num) == 0U) { in set_gpio_bit()
60 uint32_t val = 0U; in clr_gpio_bit() local
[all …]
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| /trusted-firmware-a-latest/plat/nvidia/tegra/drivers/flowctrl/ |
| D | flowctrl.c | 47 static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) in tegra_fc_cc4_ctrl() argument
49 mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); in tegra_fc_cc4_ctrl()
50 val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); in tegra_fc_cc4_ctrl()
53 static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) in tegra_fc_cpu_csr() argument
55 mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); in tegra_fc_cpu_csr()
56 val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); in tegra_fc_cpu_csr()
59 static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) in tegra_fc_halt_cpu() argument
61 mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); in tegra_fc_halt_cpu()
62 val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); in tegra_fc_halt_cpu()
67 uint32_t val; in tegra_fc_prepare_suspend() local
[all …]
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| /trusted-firmware-a-latest/drivers/imx/uart/ |
| D | imx_uart.c | 55 static void write_reg(uintptr_t base, uint32_t offset, uint32_t val) in write_reg() argument
57 mmio_write_32(base + offset, val); in write_reg()
68 uint32_t val; in console_imx_uart_core_init() local
74 val = read_reg(base_addr, IMX_UART_CR2_OFFSET); in console_imx_uart_core_init()
75 } while (!(val & IMX_UART_CR2_SRST)); in console_imx_uart_core_init()
81 val = (IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN | in console_imx_uart_core_init()
83 write_reg(base_addr, IMX_UART_CR2_OFFSET, val); in console_imx_uart_core_init()
86 val = IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL; in console_imx_uart_core_init()
87 write_reg(base_addr, IMX_UART_CR3_OFFSET, val); in console_imx_uart_core_init()
93 val = IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) | in console_imx_uart_core_init()
[all …]
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| /trusted-firmware-a-latest/plat/hisilicon/hikey/ |
| D | hisi_ipc.c | 40 unsigned int val = 0, cpu_val = 0; in hisi_cpus_pd_in_cluster_besides_curr() local
43 val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR); in hisi_cpus_pd_in_cluster_besides_curr()
44 val = val >> (cluster * 16); in hisi_cpus_pd_in_cluster_besides_curr()
51 cpu_val = (val >> (i * 4)) & 0xF; in hisi_cpus_pd_in_cluster_besides_curr()
61 unsigned int val; in hisi_cpus_powered_off_besides_curr() local
63 val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR); in hisi_cpus_powered_off_besides_curr()
64 return (val == (0x8 << (cpu * 4))); in hisi_cpus_powered_off_besides_curr()
100 unsigned int val = 0; in hisi_ipc_cpu_on_off() local
109 val = mmio_read_32(ACPU_CORE_POWERDOWN_FLAGS_ADDR); in hisi_ipc_cpu_on_off()
110 val |= (0x01 << offset); in hisi_ipc_cpu_on_off()
[all …]
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t210/ |
| D | plat_psci_handlers.c | 108 uint32_t bpmp_reply, data[3], val; in tegra_soc_get_target_pwr_state() local
139 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); in tegra_soc_get_target_pwr_state()
140 if (val == ENABLE_CLOSED_LOOP) { in tegra_soc_get_target_pwr_state()
204 uint32_t val; in tegra_soc_pwr_domain_suspend() local
239 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); in tegra_soc_pwr_domain_suspend()
240 val |= PINMUX_PWM_TRISTATE; in tegra_soc_pwr_domain_suspend()
241 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); in tegra_soc_pwr_domain_suspend()
275 uint32_t val, mask; in tegra_reset_all_dma_masters() local
280 val = GPU_RESET_BIT; in tegra_reset_all_dma_masters()
281 mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val); in tegra_reset_all_dma_masters()
[all …]
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t210/drivers/se/ |
| D | security_engine.c | 144 uint32_t val = 0; in tegra_se_operation_complete() local
149 val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET); in tegra_se_operation_complete()
150 for (timeout = 0; (SE_INT_OP_DONE(val) == SE_INT_OP_DONE_CLEAR) && in tegra_se_operation_complete()
153 val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET); in tegra_se_operation_complete()
164 val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET); in tegra_se_operation_complete()
165 for (timeout = 0; (val != 0U) && (timeout < TIMEOUT_100MS); in tegra_se_operation_complete()
168 val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET); in tegra_se_operation_complete()
180 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
181 for (timeout = 0; ((val & (ARAHB_MST_ID_SE_MASK | ARAHB_MST_ID_SE2_MASK)) != 0U) && in tegra_se_operation_complete()
184 val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET); in tegra_se_operation_complete()
[all …]
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| /trusted-firmware-a-latest/drivers/arm/gic/v2/ |
| D | gicv2_private.h | 46 uint8_t val = target & GIC_TARGET_CPU_MASK; in gicd_set_itargetsr() local
48 mmio_write_8(base + GICD_ITARGETSR + id, val); in gicd_set_itargetsr()
51 static inline void gicd_write_sgir(uintptr_t base, unsigned int val) in gicd_write_sgir() argument
53 mmio_write_32(base + GICD_SGIR, val); in gicd_write_sgir()
114 static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) in gicc_write_ctlr() argument
116 mmio_write_32(base + GICC_CTLR, val); in gicc_write_ctlr()
119 static inline void gicc_write_pmr(uintptr_t base, unsigned int val) in gicc_write_pmr() argument
121 mmio_write_32(base + GICC_PMR, val); in gicc_write_pmr()
124 static inline void gicc_write_BPR(uintptr_t base, unsigned int val) in gicc_write_BPR() argument
126 mmio_write_32(base + GICC_BPR, val); in gicc_write_BPR()
[all …]
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| /trusted-firmware-a-latest/drivers/nxp/csu/ |
| D | csu.c | 19 uint32_t val; in enable_layerscape_ns_access() local
24 val = be32toh(mmio_read_32((uintptr_t)reg)); in enable_layerscape_ns_access()
26 val &= 0x0000ffffU; in enable_layerscape_ns_access()
27 val |= csu_ns_dev[i].val << 16U; in enable_layerscape_ns_access()
29 val &= 0xffff0000U; in enable_layerscape_ns_access()
30 val |= csu_ns_dev[i].val; in enable_layerscape_ns_access()
32 mmio_write_32((uintptr_t)reg, htobe32(val)); in enable_layerscape_ns_access()
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| /trusted-firmware-a-latest/include/drivers/nxp/smmu/ |
| D | nxp_smmu.h | 22 uint32_t val; in bypass_smmu() local
24 val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) & in bypass_smmu()
26 mmio_write_32((smmu_base_addr + SMMU_SCR0), val); in bypass_smmu()
28 val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & in bypass_smmu()
30 mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); in bypass_smmu()
35 uint32_t val; in smmu_cache_unlock() local
37 val = mmio_read_32((smmu_base_addr + SMMU_SACR)); in smmu_cache_unlock()
38 val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT; in smmu_cache_unlock()
39 mmio_write_32((smmu_base_addr + SMMU_SACR), val); in smmu_cache_unlock()
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/ |
| D | gpc.c | 71 uint32_t val = gpc_saved_imrs[core_id + imr_idx * 4]; in gpc_restore_imr_lpm() local
75 mmio_write_32(reg, val); in gpc_restore_imr_lpm()
111 unsigned int val; in imx_gpc_hwirq_mask() local
119 val = mmio_read_32(reg); in imx_gpc_hwirq_mask()
120 val |= 1 << hwirq % 32; in imx_gpc_hwirq_mask()
121 mmio_write_32(reg, val); in imx_gpc_hwirq_mask()
128 unsigned int val; in imx_gpc_hwirq_unmask() local
136 val = mmio_read_32(reg); in imx_gpc_hwirq_unmask()
137 val &= ~(1 << hwirq % 32); in imx_gpc_hwirq_unmask()
138 mmio_write_32(reg, val); in imx_gpc_hwirq_unmask()
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| /trusted-firmware-a-latest/plat/intel/soc/agilex/soc/ |
| D | agilex_pinmux.c | 191 uint32_t val; in config_fpgaintf_mod() local
193 val = 0; in config_fpgaintf_mod()
195 val |= AGX_PINMUX_NAND_USEFPGA_VAL; in config_fpgaintf_mod()
197 val |= AGX_PINMUX_SDMMC_USEFPGA_VAL; in config_fpgaintf_mod()
199 val |= AGX_PINMUX_SPIM0_USEFPGA_VAL; in config_fpgaintf_mod()
201 val |= AGX_PINMUX_SPIM1_USEFPGA_VAL; in config_fpgaintf_mod()
202 mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), val); in config_fpgaintf_mod()
204 val = 0; in config_fpgaintf_mod()
206 val |= AGX_PINMUX_EMAC0_USEFPGA_VAL; in config_fpgaintf_mod()
208 val |= AGX_PINMUX_EMAC1_USEFPGA_VAL; in config_fpgaintf_mod()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/drivers/se/ |
| D | se.c | 55 uint32_t val = 0, timeout = 0, sha_status, aes_status; in tegra_se_is_operation_complete() local
64 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); in tegra_se_is_operation_complete()
65 se_is_busy = ((val & CTX_SAVE_AUTO_SE_BUSY) != 0U); in tegra_se_is_operation_complete()
101 uint32_t val = 0, timeout = 0; in tegra_se_is_ready() local
106 val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS); in tegra_se_is_ready()
107 se_is_ready = (val == CTX_SAVE_AUTO_SE_READY); in tegra_se_is_ready()
195 uint32_t val = 0U; in tegra_se_sha256_hash_operation_complete() local
198 val = tegra_se_read_32(SE0_INT_STATUS_REG_OFFSET); in tegra_se_sha256_hash_operation_complete()
199 while (SE0_INT_OP_DONE(val) == SE0_INT_OP_DONE_CLEAR) { in tegra_se_sha256_hash_operation_complete()
200 val = tegra_se_read_32(SE0_INT_STATUS_REG_OFFSET); in tegra_se_sha256_hash_operation_complete()
[all …]
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| /trusted-firmware-a-latest/plat/mediatek/common/lpm/ |
| D | mt_lp_api.c | 11 int ret, val; in mt_audio_update() local
16 val = (type == AUDIO_AFE_ENTER) ? 1 : 0; in mt_audio_update()
17 ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_FMAUDIO, &val); in mt_audio_update()
21 val = (type == AUDIO_DSP_ENTER) ? 1 : 0; in mt_audio_update()
22 ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_ADSP, &val); in mt_audio_update()
34 int ret, val; in mtk_usb_update() local
39 val = (type == LPM_USB_ENTER) ? 1 : 0; in mtk_usb_update()
40 ret = mt_lp_rm_do_update(-1, PLAT_RC_IS_USB_INFRA, &val); in mtk_usb_update()
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| /trusted-firmware-a-latest/lib/libfdt/ |
| D | fdt_addresses.c | 17 uint32_t val; in fdt_cells() local
27 val = fdt32_to_cpu(*c); in fdt_cells()
28 if (val > FDT_MAX_NCELLS) in fdt_cells()
31 return (int)val; in fdt_cells()
36 int val; in fdt_address_cells() local
38 val = fdt_cells(fdt, nodeoffset, "#address-cells"); in fdt_address_cells()
39 if (val == 0) in fdt_address_cells()
41 if (val == -FDT_ERR_NOTFOUND) in fdt_address_cells()
43 return val; in fdt_address_cells()
48 int val; in fdt_size_cells() local
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| /trusted-firmware-a-latest/drivers/arm/gic/v3/ |
| D | gic600ae_fmu_helpers.c | 19 #define GIC_FMU_WRITE_32(base, reg, val) \ argument
27 mmio_write_32((base) + (reg), (val)); \
31 #define GIC_FMU_WRITE_64(base, reg, n, val) \ argument
42 mmio_write_32((base) + reg##_LO + (n * 64), (val)); \
43 mmio_write_32((base) + reg##_HI + (n * 64), (val)); \
66 #define GIC_FMU_WRITE_ON_IDLE_32(base, reg, val) \ argument
71 GIC_FMU_WRITE_32(base, reg, val); \
76 #define GIC_FMU_WRITE_ON_IDLE_64(base, reg, n, val) \ argument
81 GIC_FMU_WRITE_64(base, reg, n, val); \
203 void gic_fmu_write_errctlr(uintptr_t base, unsigned int n, uint64_t val) in gic_fmu_write_errctlr() argument
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| /trusted-firmware-a-latest/plat/hisilicon/hikey960/drivers/pwrc/ |
| D | hisi_pwrc.c | 131 unsigned int val; in hisi_get_cpuidle_flag() local
133 val = mmio_read_32(CPUIDLE_FLAG_REG(cluster)); in hisi_get_cpuidle_flag()
134 val &= 0xF; in hisi_get_cpuidle_flag()
136 return val; in hisi_get_cpuidle_flag()
168 unsigned int val; in hisi_set_cluster_pwdn_flag() local
172 val = mmio_read_32(REG_SCBAKDATA3_OFFSET); in hisi_set_cluster_pwdn_flag()
173 val &= ~(0x3U << ((2 * cluster) + 28)); in hisi_set_cluster_pwdn_flag()
174 val |= (value << (2 * cluster)); in hisi_set_cluster_pwdn_flag()
175 mmio_write_32(REG_SCBAKDATA3_OFFSET, val); in hisi_set_cluster_pwdn_flag()
182 unsigned int val; in hisi_get_cpu_boot_flag() local
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