55 static void write_reg(uintptr_t base, uint32_t offset, uint32_t val)  in write_reg()  argument
57 	mmio_write_32(base + offset, val);  in write_reg()
68 	uint32_t val;  in console_imx_uart_core_init()  local
74 		val = read_reg(base_addr, IMX_UART_CR2_OFFSET);  in console_imx_uart_core_init()
75 	} while (!(val & IMX_UART_CR2_SRST));  in console_imx_uart_core_init()
81 	val = (IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN |  in console_imx_uart_core_init()
83 	write_reg(base_addr, IMX_UART_CR2_OFFSET, val);  in console_imx_uart_core_init()
86 	val = IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL;  in console_imx_uart_core_init()
87 	write_reg(base_addr, IMX_UART_CR3_OFFSET, val);  in console_imx_uart_core_init()
93 	val = IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) |  in console_imx_uart_core_init()
97 		val |= IMX_UART_FCR_DCEDTE;  in console_imx_uart_core_init()
99 	write_reg(base_addr, IMX_UART_FCR_OFFSET, val);  in console_imx_uart_core_init()
116 	val = ((uart_clk / clk_div[clk_idx].bmr_div) / baud_rate) - 1;  in console_imx_uart_core_init()
117 	write_reg(base_addr, IMX_UART_BMR_OFFSET, val);  in console_imx_uart_core_init()
134 	uint32_t val;  in console_imx_uart_core_putc()  local
144 		val = read_reg(base_addr, IMX_UART_STAT2_OFFSET);  in console_imx_uart_core_putc()
145 	} while (!(val & IMX_UART_STAT2_TXDC));  in console_imx_uart_core_putc()
160 	uint32_t val;  in console_imx_uart_core_getc()  local
162 	val = read_reg(base_addr, IMX_UART_TS_OFFSET);  in console_imx_uart_core_getc()
163 	if (val & IMX_UART_TS_RXEMPTY)  in console_imx_uart_core_getc()
166 	val = read_reg(base_addr, IMX_UART_RXD_OFFSET);  in console_imx_uart_core_getc()
167 	return (int)(val & 0x000000FF);  in console_imx_uart_core_getc()