Lines Matching refs:val
79 unsigned int val; in brcm_stingray_dma_pl330_init() local
93 val = (DMAC_STREAM_ID << DMAC_SID_SHIFT); in brcm_stingray_dma_pl330_init()
94 mmio_write_32(ICFG_DMAC_SID_ARADDR_CONTROL, val); in brcm_stingray_dma_pl330_init()
95 mmio_write_32(ICFG_DMAC_SID_AWADDR_CONTROL, val); in brcm_stingray_dma_pl330_init()
313 unsigned int val; in brcm_stingray_amac_init() local
318 val = SR_SID_VAL(0x3, 0x0, 0x4) << ICFG_AMAC_SID_SHIFT; in brcm_stingray_amac_init()
319 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_AWADDR_OFFSET, val); in brcm_stingray_amac_init()
320 mmio_write_32(icfg_amac_sid + ICFG_AMAC_SID_ARADDR_OFFSET, val); in brcm_stingray_amac_init()
393 unsigned int val; in brcm_stingray_smmu_init() local
400 val = mmio_read_32(smmu_base + 0x0); in brcm_stingray_smmu_init()
401 val |= (0x1 << 12); in brcm_stingray_smmu_init()
402 mmio_write_32(smmu_base + 0x0, val); in brcm_stingray_smmu_init()
493 unsigned int val; in brcm_stingray_scr_init() local
502 val = mmio_read_32(scr_base + 0x0); in brcm_stingray_scr_init()
503 VERBOSE(" - set tbu0_config=0x%x\n", val); in brcm_stingray_scr_init()
507 val = mmio_read_32(scr_base + 0x4); in brcm_stingray_scr_init()
508 VERBOSE(" - set tbu1_config=0x%x\n", val); in brcm_stingray_scr_init()
512 val = mmio_read_32(scr_base + 0x8); in brcm_stingray_scr_init()
513 VERBOSE(" - set tbu2_config=0x%x\n", val); in brcm_stingray_scr_init()
517 val = mmio_read_32(scr_base + 0xc); in brcm_stingray_scr_init()
518 VERBOSE(" - set tbu3_config=0x%x\n", val); in brcm_stingray_scr_init()
522 val = mmio_read_32(scr_base + 0x10); in brcm_stingray_scr_init()
523 VERBOSE(" - set tbu4_config=0x%x\n", val); in brcm_stingray_scr_init()
527 val = mmio_read_32(scr_base + 0x14); in brcm_stingray_scr_init()
528 VERBOSE(" - set gic_config=0x%x\n", val); in brcm_stingray_scr_init()
535 unsigned int val; in brcm_stingray_hsls_tzpcprot_init() local
541 val = 0; in brcm_stingray_hsls_tzpcprot_init()
542 val |= BIT(6); /* SDIO1 */ in brcm_stingray_hsls_tzpcprot_init()
543 val |= BIT(5); /* SDIO0 */ in brcm_stingray_hsls_tzpcprot_init()
544 val |= BIT(0); /* AMAC */ in brcm_stingray_hsls_tzpcprot_init()
545 mmio_write_32(tzpcdecprot_base + 0x810, val); in brcm_stingray_hsls_tzpcprot_init()
586 unsigned int val; in brcm_stingray_audio_init() local
603 val = SR_SID_VAL(0x3, 0x0, 0x1) << ICFG_AUDIO_SID_SHIFT; in brcm_stingray_audio_init()
604 mmio_write_32(icfg_audio_sid + ICFG_AUDIO_SID_AWADDR_OFFSET, val); in brcm_stingray_audio_init()
605 mmio_write_32(icfg_audio_sid + ICFG_AUDIO_SID_ARADDR_OFFSET, val); in brcm_stingray_audio_init()
697 unsigned int val; in brcm_stingray_security_init() local
699 val = mmio_read_32(SCR_GPV_SMMU_NS); in brcm_stingray_security_init()
700 val |= BIT(0); /* SMMU NS = 1 */ in brcm_stingray_security_init()
701 mmio_write_32(SCR_GPV_SMMU_NS, val); in brcm_stingray_security_init()
703 val = mmio_read_32(SCR_GPV_GIC500_NS); in brcm_stingray_security_init()
704 val |= BIT(0); /* GIC-500 NS = 1 */ in brcm_stingray_security_init()
705 mmio_write_32(SCR_GPV_GIC500_NS, val); in brcm_stingray_security_init()
707 val = mmio_read_32(HSLS_GPV_NOR_S0_NS); in brcm_stingray_security_init()
708 val |= BIT(0); /* NOR SLAVE NS = 1 */ in brcm_stingray_security_init()
709 mmio_write_32(HSLS_GPV_NOR_S0_NS, val); in brcm_stingray_security_init()
711 val = mmio_read_32(HSLS_GPV_IDM1_NS); in brcm_stingray_security_init()
712 val |= BIT(0); /* DMA IDM NS = 1 */ in brcm_stingray_security_init()
713 val |= BIT(1); /* I2S IDM NS = 1 */ in brcm_stingray_security_init()
714 val |= BIT(2); /* AMAC IDM NS = 1 */ in brcm_stingray_security_init()
715 val |= BIT(3); /* SDIO0 IDM NS = 1 */ in brcm_stingray_security_init()
716 val |= BIT(4); /* SDIO1 IDM NS = 1 */ in brcm_stingray_security_init()
717 val |= BIT(5); /* DS_3 IDM NS = 1 */ in brcm_stingray_security_init()
718 mmio_write_32(HSLS_GPV_IDM1_NS, val); in brcm_stingray_security_init()
720 val = mmio_read_32(HSLS_GPV_IDM2_NS); in brcm_stingray_security_init()
721 val |= BIT(2); /* QSPI IDM NS = 1 */ in brcm_stingray_security_init()
722 val |= BIT(1); /* NOR IDM NS = 1 */ in brcm_stingray_security_init()
723 val |= BIT(0); /* NAND IDM NS = 1 */ in brcm_stingray_security_init()
724 mmio_write_32(HSLS_GPV_IDM2_NS, val); in brcm_stingray_security_init()
726 val = mmio_read_32(HSLS_GPV_APBY_NS); in brcm_stingray_security_init()
727 val |= BIT(10); /* I2S NS = 1 */ in brcm_stingray_security_init()
728 val |= BIT(4); /* IOPAD NS = 1 */ in brcm_stingray_security_init()
729 val |= 0xf; /* UARTx NS = 1 */ in brcm_stingray_security_init()
730 mmio_write_32(HSLS_GPV_APBY_NS, val); in brcm_stingray_security_init()
732 val = mmio_read_32(HSLS_GPV_APBZ_NS); in brcm_stingray_security_init()
733 val |= BIT(2); /* RNG NS = 1 */ in brcm_stingray_security_init()
734 mmio_write_32(HSLS_GPV_APBZ_NS, val); in brcm_stingray_security_init()
736 val = mmio_read_32(HSLS_GPV_APBS_NS); in brcm_stingray_security_init()
737 val |= 0x3; /* SPIx NS = 1 */ in brcm_stingray_security_init()
738 mmio_write_32(HSLS_GPV_APBS_NS, val); in brcm_stingray_security_init()
740 val = mmio_read_32(HSLS_GPV_APBR_NS); in brcm_stingray_security_init()
741 val |= BIT(7); /* QSPI APB NS = 1 */ in brcm_stingray_security_init()
742 val |= BIT(6); /* NAND APB NS = 1 */ in brcm_stingray_security_init()
743 val |= BIT(5); /* NOR APB NS = 1 */ in brcm_stingray_security_init()
744 val |= BIT(4); /* AMAC APB NS = 1 */ in brcm_stingray_security_init()
745 val |= BIT(1); /* DMA S1 APB NS = 1 */ in brcm_stingray_security_init()
746 mmio_write_32(HSLS_GPV_APBR_NS, val); in brcm_stingray_security_init()
748 val = mmio_read_32(HSLS_SDIO0_SLAVE_NS); in brcm_stingray_security_init()
749 val |= BIT(0); /* SDIO0 NS = 1 */ in brcm_stingray_security_init()
750 mmio_write_32(HSLS_SDIO0_SLAVE_NS, val); in brcm_stingray_security_init()
752 val = mmio_read_32(HSLS_SDIO1_SLAVE_NS); in brcm_stingray_security_init()
753 val |= BIT(0); /* SDIO1 NS = 1 */ in brcm_stingray_security_init()
754 mmio_write_32(HSLS_SDIO1_SLAVE_NS, val); in brcm_stingray_security_init()
756 val = mmio_read_32(HSLS_GPV_APBX_NS); in brcm_stingray_security_init()
757 val |= BIT(14); /* SMBUS1 NS = 1 */ in brcm_stingray_security_init()
758 val |= BIT(13); /* GPIO NS = 1 */ in brcm_stingray_security_init()
759 val |= BIT(12); /* WDT NS = 1 */ in brcm_stingray_security_init()
760 val |= BIT(11); /* SMBUS0 NS = 1 */ in brcm_stingray_security_init()
761 val |= BIT(10); /* Timer7 NS = 1 */ in brcm_stingray_security_init()
762 val |= BIT(9); /* Timer6 NS = 1 */ in brcm_stingray_security_init()
763 val |= BIT(8); /* Timer5 NS = 1 */ in brcm_stingray_security_init()
764 val |= BIT(7); /* Timer4 NS = 1 */ in brcm_stingray_security_init()
765 val |= BIT(6); /* Timer3 NS = 1 */ in brcm_stingray_security_init()
766 val |= BIT(5); /* Timer2 NS = 1 */ in brcm_stingray_security_init()
767 val |= BIT(4); /* Timer1 NS = 1 */ in brcm_stingray_security_init()
768 val |= BIT(3); /* Timer0 NS = 1 */ in brcm_stingray_security_init()
769 val |= BIT(2); /* MDIO NS = 1 */ in brcm_stingray_security_init()
770 val |= BIT(1); /* PWM NS = 1 */ in brcm_stingray_security_init()
771 mmio_write_32(HSLS_GPV_APBX_NS, val); in brcm_stingray_security_init()
773 val = mmio_read_32(HSLS_GPV_QSPI_S0_NS); in brcm_stingray_security_init()
774 val |= BIT(0); /* QSPI NS = 1 */ in brcm_stingray_security_init()
775 mmio_write_32(HSLS_GPV_QSPI_S0_NS, val); in brcm_stingray_security_init()
778 val = 0x1; /* FS4 Crypto rm_slave */ in brcm_stingray_security_init()
779 mmio_write_32(FS4_CRYPTO_GPV_RM_SLAVE_NS, val); in brcm_stingray_security_init()
780 val = 0x1; /* FS4 Crypto apb_switch */ in brcm_stingray_security_init()
781 mmio_write_32(FS4_CRYPTO_GPV_APB_SWITCH_NS, val); in brcm_stingray_security_init()
783 val = 0x1; /* FS4 Raid rm_slave */ in brcm_stingray_security_init()
784 mmio_write_32(FS4_RAID_GPV_RM_SLAVE_NS, val); in brcm_stingray_security_init()
785 val = 0x1; /* FS4 Raid apb_switch */ in brcm_stingray_security_init()
786 mmio_write_32(FS4_RAID_GPV_APB_SWITCH_NS, val); in brcm_stingray_security_init()
788 val = 0x1; /* FS4 Crypto IDM */ in brcm_stingray_security_init()
789 mmio_write_32(FS4_CRYPTO_IDM_NS, val); in brcm_stingray_security_init()
790 val = 0x1; /* FS4 RAID IDM */ in brcm_stingray_security_init()
791 mmio_write_32(FS4_RAID_IDM_NS, val); in brcm_stingray_security_init()