108 	uint32_t bpmp_reply, data[3], val;  in tegra_soc_get_target_pwr_state()  local
139 			val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL);  in tegra_soc_get_target_pwr_state()
140 			if (val == ENABLE_CLOSED_LOOP) {  in tegra_soc_get_target_pwr_state()
204 	uint32_t val;  in tegra_soc_pwr_domain_suspend()  local
239 				val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);  in tegra_soc_pwr_domain_suspend()
240 				val |= PINMUX_PWM_TRISTATE;  in tegra_soc_pwr_domain_suspend()
241 				mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);  in tegra_soc_pwr_domain_suspend()
275 	uint32_t val, mask;  in tegra_reset_all_dma_masters()  local
280 	val = GPU_RESET_BIT;  in tegra_reset_all_dma_masters()
281 	mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val);  in tegra_reset_all_dma_masters()
283 	val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |  in tegra_reset_all_dma_masters()
285 	mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val);  in tegra_reset_all_dma_masters()
287 	val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |  in tegra_reset_all_dma_masters()
290 	mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val);  in tegra_reset_all_dma_masters()
292 	val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;  in tegra_reset_all_dma_masters()
293 	mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val);  in tegra_reset_all_dma_masters()
295 	val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |  in tegra_reset_all_dma_masters()
297 	mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val);  in tegra_reset_all_dma_masters()
299 	val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;  in tegra_reset_all_dma_masters()
300 	mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val);  in tegra_reset_all_dma_masters()
306 	val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);  in tegra_reset_all_dma_masters()
308 	if ((val & mask) != mask)  in tegra_reset_all_dma_masters()
313 	val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y);  in tegra_reset_all_dma_masters()
314 	if ((val & mask) != mask)  in tegra_reset_all_dma_masters()
320 	val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L);  in tegra_reset_all_dma_masters()
321 	if ((val & mask) != mask)  in tegra_reset_all_dma_masters()
325 	val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H);  in tegra_reset_all_dma_masters()
326 	if ((val & mask) != mask)  in tegra_reset_all_dma_masters()
331 	val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U);  in tegra_reset_all_dma_masters()
332 	if ((val & mask) != mask)  in tegra_reset_all_dma_masters()
335 	val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V);  in tegra_reset_all_dma_masters()
337 	if ((val & mask) != mask)  in tegra_reset_all_dma_masters()
348 	uint32_t val;  in tegra_soc_pwr_domain_power_down_wfi()  local
399 			val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);  in tegra_soc_pwr_domain_power_down_wfi()
400 			val &= ~PMC_SECURITY_EN_BIT;  in tegra_soc_pwr_domain_power_down_wfi()
401 			mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);  in tegra_soc_pwr_domain_power_down_wfi()
417 				val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);  in tegra_soc_pwr_domain_power_down_wfi()
418 			} while (val != SIGN_OF_LIFE);  in tegra_soc_pwr_domain_power_down_wfi()
437 	uint32_t val, entrypoint = 0;  in tegra_soc_pwr_domain_on_finish()  local
443 		val = read_l2ctlr_el1();  in tegra_soc_pwr_domain_on_finish()
444 		val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;  in tegra_soc_pwr_domain_on_finish()
445 		write_l2ctlr_el1(val);  in tegra_soc_pwr_domain_on_finish()
470 		val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG);  in tegra_soc_pwr_domain_on_finish()
471 		val &= ~ENABLE_UNSUP_TX_ERRORS;  in tegra_soc_pwr_domain_on_finish()
472 		val |= ENABLE_WRAP_TO_INCR_BURSTS;  in tegra_soc_pwr_domain_on_finish()
473 		mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val);  in tegra_soc_pwr_domain_on_finish()
498 			val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);  in tegra_soc_pwr_domain_on_finish()
499 			val |= PMC_SECURITY_EN_BIT;  in tegra_soc_pwr_domain_on_finish()
500 			mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);  in tegra_soc_pwr_domain_on_finish()
515 				val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);  in tegra_soc_pwr_domain_on_finish()
516 				val &= ~PINMUX_PWM_TRISTATE;  in tegra_soc_pwr_domain_on_finish()
517 				mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);  in tegra_soc_pwr_domain_on_finish()
520 				val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);  in tegra_soc_pwr_domain_on_finish()
521 				assert((val & PINMUX_PWM_TRISTATE) == 0U);  in tegra_soc_pwr_domain_on_finish()