99 static void paxc_rc_cfg_write(uint32_t where, uint32_t val)  in paxc_rc_cfg_write()  argument
103 	mmio_write_32(PAXC_BASE + PAXC_CFG_IND_DATA_OFFSET, val);  in paxc_rc_cfg_write()
118 	uint32_t val;  in paxc_cfg_link_cap()  local
120 	val = paxc_rc_cfg_read(PAXC_CFG_LINK_CAP_OFFSET);  in paxc_cfg_link_cap()
121 	val &= ~(PAXC_RC_LINK_CAP_SPD_MASK | PAXC_RC_LINK_CAP_WIDTH_MASK);  in paxc_cfg_link_cap()
122 	val |= (PAXC_RC_LINK_CAP_SPD << PAXC_RC_LINK_CAP_SPD_SHIFT) |  in paxc_cfg_link_cap()
124 	paxc_rc_cfg_write(PAXC_CFG_LINK_CAP_OFFSET, val);  in paxc_cfg_link_cap()
132 	uint32_t val;  in paxc_cfg_id()  local
134 	val = (PAXC_RC_VENDOR_ID << PAXC_RC_VENDOR_ID_SHIFT) |  in paxc_cfg_id()
136 	paxc_rc_cfg_write(PAXC_CFG_ID_OFFSET, val);  in paxc_cfg_id()
142 	unsigned int val;  in paxc_init()  local
144 	val = mmio_read_32(MHB_MEM_PWR_STATUS_PAXC);  in paxc_init()
145 	if ((val & MHB_PWR_STATUS_MASK) != MHB_PWR_STATUS_MASK) {  in paxc_init()
162 	val = 0xff;  in paxc_init()
165 	val = 0x0;  in paxc_init()
169 			      val);  in paxc_init()
214 	unsigned int val;  in paxc_mhb_ns_init()  local
221 	val = mmio_read_32(mhb_nic_gpv + MHB_NIC_PAXC_AXI_NS);  in paxc_mhb_ns_init()
222 	val |= 0x1;  in paxc_mhb_ns_init()
223 	mmio_write_32(mhb_nic_gpv + MHB_NIC_PAXC_AXI_NS, val);  in paxc_mhb_ns_init()
226 	val = mmio_read_32(mhb_nic_gpv + MHB_NIC_IDM_NS);  in paxc_mhb_ns_init()
227 	val |= (0x1 << MHB_NIC_PAXC_APB_S_IDM_SHIFT);  in paxc_mhb_ns_init()
228 	val |= (0x1 << MHB_NIC_EP_APB_S_IDM_SHIFT);  in paxc_mhb_ns_init()
229 	val |= (0x1 << MHB_NIC_MHB_APB_S_IDM_SHIFT);  in paxc_mhb_ns_init()
230 	val |= (0x1 << MHB_NIC_PAXC_AXI_S_IDM_SHIFT);  in paxc_mhb_ns_init()
231 	val |= (0x1 << MHB_NIC_PCIE_AXI_S_IDM_SHIFT);  in paxc_mhb_ns_init()
232 	val |= (0x1 << MHB_NIC_NITRO_AXI_S_IDM_SHIFT);  in paxc_mhb_ns_init()
233 	mmio_write_32(mhb_nic_gpv + MHB_NIC_IDM_NS, val);  in paxc_mhb_ns_init()
236 	val = mmio_read_32(mhb_nic_gpv + MHB_NIC_MHB_APB_NS);  in paxc_mhb_ns_init()
237 	val |= 0x1;  in paxc_mhb_ns_init()
238 	mmio_write_32(mhb_nic_gpv + MHB_NIC_MHB_APB_NS, val);  in paxc_mhb_ns_init()
241 	val = mmio_read_32(mhb_nic_gpv + MHB_NIC_NITRO_AXI_NS);  in paxc_mhb_ns_init()
242 	val |= 0x1;  in paxc_mhb_ns_init()
243 	mmio_write_32(mhb_nic_gpv + MHB_NIC_NITRO_AXI_NS, val);  in paxc_mhb_ns_init()
246 	val = mmio_read_32(mhb_nic_gpv + MHB_NIC_PCIE_AXI_NS);  in paxc_mhb_ns_init()
247 	val |= 0x1;  in paxc_mhb_ns_init()
248 	mmio_write_32(mhb_nic_gpv + MHB_NIC_PCIE_AXI_NS, val);  in paxc_mhb_ns_init()
251 	val = mmio_read_32(mhb_nic_gpv + MHB_NIC_PAXC_APB_NS);  in paxc_mhb_ns_init()
252 	val |= 0x1;  in paxc_mhb_ns_init()
253 	mmio_write_32(mhb_nic_gpv + MHB_NIC_PAXC_APB_NS, val);  in paxc_mhb_ns_init()
256 	val = mmio_read_32(mhb_nic_gpv + MHB_NIC_EP_APB_NS);  in paxc_mhb_ns_init()
257 	val |= 0x1;  in paxc_mhb_ns_init()
258 	mmio_write_32(mhb_nic_gpv + MHB_NIC_EP_APB_NS, val);  in paxc_mhb_ns_init()