71 	uint32_t val = gpc_saved_imrs[core_id + imr_idx * 4];  in gpc_restore_imr_lpm()  local
75 	mmio_write_32(reg, val);  in gpc_restore_imr_lpm()
111 	unsigned int val;  in imx_gpc_hwirq_mask()  local
119 	val = mmio_read_32(reg);  in imx_gpc_hwirq_mask()
120 	val |= 1 << hwirq % 32;  in imx_gpc_hwirq_mask()
121 	mmio_write_32(reg, val);  in imx_gpc_hwirq_mask()
128 	unsigned int val;  in imx_gpc_hwirq_unmask()  local
136 	val = mmio_read_32(reg);  in imx_gpc_hwirq_unmask()
137 	val &= ~(1 << hwirq % 32);  in imx_gpc_hwirq_unmask()
138 	mmio_write_32(reg, val);  in imx_gpc_hwirq_unmask()
186 	unsigned int val;  in imx_gpc_set_affinity()  local
198 	val = mmio_read_32(reg);  in imx_gpc_set_affinity()
199 	val &= ~(1 << hwirq % 32);  in imx_gpc_set_affinity()
200 	mmio_write_32(reg, val);  in imx_gpc_set_affinity()
208 			val = mmio_read_32(reg);  in imx_gpc_set_affinity()
209 			val |= (1 << hwirq % 32);  in imx_gpc_set_affinity()
210 			mmio_write_32(reg, val);  in imx_gpc_set_affinity()
276 	uint32_t val;  in imx_set_cluster_powerdown()  local
279 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_set_cluster_powerdown()
280 		val |= A53_LPM_STOP; /* enable C0-C1's STOP mode */  in imx_set_cluster_powerdown()
281 		val &= ~CPU_CLOCK_ON_LPM; /* disable CPU clock in LPM mode */  in imx_set_cluster_powerdown()
282 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_set_cluster_powerdown()
288 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);  in imx_set_cluster_powerdown()
289 		val &= ~EN_L2_WFI_PDN;  in imx_set_cluster_powerdown()
290 		val |= L2PGE | EN_PLAT_PDN;  in imx_set_cluster_powerdown()
291 		val &= ~COREx_IRQ_WUP(last_core); /* disable IRQ PUP for last core */  in imx_set_cluster_powerdown()
292 		val |= COREx_LPM_PUP(last_core); /* enable LPM PUP for last core */  in imx_set_cluster_powerdown()
293 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);  in imx_set_cluster_powerdown()
306 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_set_cluster_powerdown()
307 		val &= ~A53_LPM_MASK; /* clear the C0~1 LPM */  in imx_set_cluster_powerdown()
308 		val |= CPU_CLOCK_ON_LPM; /* disable cpu clock in LPM */  in imx_set_cluster_powerdown()
309 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_set_cluster_powerdown()
315 		val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD);  in imx_set_cluster_powerdown()
316 		val |= EN_L2_WFI_PDN;  in imx_set_cluster_powerdown()
317 		val &= ~(L2PGE | EN_PLAT_PDN);  in imx_set_cluster_powerdown()
318 		val &= ~COREx_LPM_PUP(last_core);  /* disable C0's LPM PUP */  in imx_set_cluster_powerdown()
319 		mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val);  in imx_set_cluster_powerdown()
386 	uint32_t val;  in imx_gpc_init()  local
408 	val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC);  in imx_gpc_init()
409 	val |= IRQ_SRC_A53_WUP;  in imx_gpc_init()
411 	val &= ~MASTER0_LPM_HSK;  in imx_gpc_init()
412 	mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val);  in imx_gpc_init()