286 	uint32_t val, link_speed;  in paxb_rc_link_init()  local
302 		val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_CAP);  in paxb_rc_link_init()
303 		val &= ~CFG_RC_LINK_CAP_WIDTH_MASK;  in paxb_rc_link_init()
304 		val |= (link_width << CFG_RC_LINK_CAP_WIDTH_SHIFT);  in paxb_rc_link_init()
305 		paxb_rc_cfg_write(core_idx, CFG_RC_LINK_CAP, val);  in paxb_rc_link_init()
308 		val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_CAP);  in paxb_rc_link_init()
309 		val &= ~CFG_RC_LINK_CAP_SPEED_MASK;  in paxb_rc_link_init()
310 		val |= link_speed << CFG_RC_LINK_CAP_SPEED_SHIFT;  in paxb_rc_link_init()
311 		paxb_rc_cfg_write(core_idx, CFG_RC_LINK_CAP, val);  in paxb_rc_link_init()
314 		val = paxb_rc_cfg_read(core_idx, CFG_RC_LINK_STATUS_CTRL_2);  in paxb_rc_link_init()
315 		val &= ~(CFG_RC_LINK_SPEED_MASK);  in paxb_rc_link_init()
316 		val |= link_speed << CFG_RC_LINK_SPEED_SHIFT;  in paxb_rc_link_init()
317 		paxb_rc_cfg_write(core_idx, CFG_RC_LINK_STATUS_CTRL_2, val);  in paxb_rc_link_init()
322 		val = paxb_rc_cfg_read(core_idx, CFG_RC_REG_PHY_CTL_10);  in paxb_rc_link_init()
323 		val &= ~(PHY_CTL_10_GEN3_MATCH_PARITY);  in paxb_rc_link_init()
324 		paxb_rc_cfg_write(core_idx, CFG_RC_REG_PHY_CTL_10, val);  in paxb_rc_link_init()
350 	uint32_t val, timeout;  in paxb_start_link_up()  local
363 			val = mmio_read_32(PAXB_OFFSET(core_idx) +  in paxb_start_link_up()
365 			if (val & PAXB_CFG_DL_ACTIVE_MASK)  in paxb_start_link_up()
394 	uint32_t val;  in pcie_core_pwron_switch()  local
402 		val = mmio_read_32(status);  in pcie_core_pwron_switch()
403 		if ((val & mask) == mask)  in pcie_core_pwron_switch()
520 			      uint32_t val)  in paxb_rc_cfg_write()  argument
525 	mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_DATA_OFFSET, val);  in paxb_rc_cfg_write()
530 	unsigned int val;  in paxb_rc_cfg_read()  local
535 	val = mmio_read_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_DATA_OFFSET);  in paxb_rc_cfg_read()
537 	return val;  in paxb_rc_cfg_read()
542 	uint32_t val, core_idx, mps;  in paxb_cfg_mps()  local
548 		val = paxb_rc_cfg_read(core_idx, CFG_RC_DEVICE_CAP);  in paxb_cfg_mps()
549 		val &= ~CFG_RC_DEVICE_CAP_MPS_MASK;  in paxb_cfg_mps()
555 		val |= mps;  in paxb_cfg_mps()
556 		paxb_rc_cfg_write(core_idx, CFG_RC_DEVICE_CAP, val);  in paxb_cfg_mps()
562 	uint32_t val, core_idx;  in paxb_cfg_dev_id()  local
576 		val = paxb_rc_cfg_read(core_idx, PCI_BRIDGE_CTRL_REG_OFFSET);  in paxb_cfg_dev_id()
577 		val &= ~PCI_CLASS_BRIDGE_MASK;  in paxb_cfg_dev_id()
578 		val |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);  in paxb_cfg_dev_id()
579 		paxb_rc_cfg_write(core_idx, PCI_BRIDGE_CTRL_REG_OFFSET, val);  in paxb_cfg_dev_id()
581 		val = (VENDOR_ID << 16) | device_id;  in paxb_cfg_dev_id()
582 		paxb_rc_cfg_write(core_idx, CFG_RC_DEV_ID, val);  in paxb_cfg_dev_id()
584 		val = (device_id << 16) | VENDOR_ID;  in paxb_cfg_dev_id()
585 		paxb_rc_cfg_write(core_idx, CFG_RC_DEV_SUBID, val);  in paxb_cfg_dev_id()
591 	uint32_t val, core_idx;  in paxb_cfg_tgt_trn()  local
603 		val = paxb_rc_cfg_read(core_idx, CFG_RC_TL_CTRL_0);  in paxb_cfg_tgt_trn()
604 		val &= ~(RC_MEM_DW_CHK_MASK);  in paxb_cfg_tgt_trn()
605 		paxb_rc_cfg_write(core_idx, CFG_RC_TL_CTRL_0, val);  in paxb_cfg_tgt_trn()
611 	uint32_t val, core_idx;  in paxb_cfg_pdl_ctrl()  local
629 		val = paxb_rc_cfg_read(core_idx, CFG_RC_PDL_CTRL_4);  in paxb_cfg_pdl_ctrl()
630 		val &= ~NPH_FC_INIT_MASK;  in paxb_cfg_pdl_ctrl()
631 		val &= ~PD_FC_INIT_MASK;  in paxb_cfg_pdl_ctrl()
632 		val = val | (nph << NPH_FC_INIT_SHIFT);  in paxb_cfg_pdl_ctrl()
633 		val = val | (pd << PD_FC_INIT_SHIFT);  in paxb_cfg_pdl_ctrl()
634 		paxb_rc_cfg_write(core_idx, CFG_RC_PDL_CTRL_4, val);  in paxb_cfg_pdl_ctrl()
636 		val = paxb_rc_cfg_read(core_idx, CFG_RC_PDL_CTRL_5);  in paxb_cfg_pdl_ctrl()
637 		val &= ~PH_INIT_MASK;  in paxb_cfg_pdl_ctrl()
638 		val = val | (ph << PH_INIT_SHIFT);  in paxb_cfg_pdl_ctrl()
639 		paxb_rc_cfg_write(core_idx, CFG_RC_PDL_CTRL_5, val);  in paxb_cfg_pdl_ctrl()
656 	uint32_t val, core_idx;  in paxb_cfg_clkreq()  local
662 		val = paxb_rc_cfg_read(core_idx, CFG_RC_CLKREQ_ENABLED);  in paxb_cfg_clkreq()
663 		val &= ~CFG_RC_CLKREQ_ENABLED_MASK;  in paxb_cfg_clkreq()
664 		paxb_rc_cfg_write(core_idx, CFG_RC_CLKREQ_ENABLED, val);  in paxb_cfg_clkreq()
670 	uint32_t val, core_idx;  in paxb_cfg_dl_active()  local
676 		val = paxb_rc_cfg_read(core_idx, CFG_LINK_CAP_RC);  in paxb_cfg_dl_active()
678 			val |= CFG_RC_DL_ACTIVE_MASK;  in paxb_cfg_dl_active()
680 			val &= ~CFG_RC_DL_ACTIVE_MASK;  in paxb_cfg_dl_active()
681 		paxb_rc_cfg_write(core_idx, CFG_LINK_CAP_RC, val);  in paxb_cfg_dl_active()
687 	uint32_t val, core_idx;  in paxb_cfg_LTR()  local
693 		val = paxb_rc_cfg_read(core_idx, CFG_ROOT_CAP_RC);  in paxb_cfg_LTR()
695 			val |= CFG_ROOT_CAP_LTR_MASK;  in paxb_cfg_LTR()
697 			val &= ~CFG_ROOT_CAP_LTR_MASK;  in paxb_cfg_LTR()
698 		paxb_rc_cfg_write(core_idx, CFG_ROOT_CAP_RC, val);  in paxb_cfg_LTR()
769 	uint32_t val;  in paxb_smmu_cfg()  local
776 		val = mmio_read_32(PCIE_PAXB_SMMU_SID_CFG + offset);  in paxb_smmu_cfg()
777 		val &= ~(0xFFF00);  in paxb_smmu_cfg()
778 		val |= (PAXB_SMMU_SID_CFG_FUN_WIDTH |  in paxb_smmu_cfg()
781 		mmio_write_32(PCIE_PAXB_SMMU_SID_CFG + offset, val);  in paxb_smmu_cfg()
782 		val = mmio_read_32(PCIE_PAXB_SMMU_SID_CFG + offset);  in paxb_smmu_cfg()
783 		VERBOSE("smmu cfg reg 0x%x\n", val);  in paxb_smmu_cfg()