Searched refs:_REG_ (Results 1 – 25 of 86) sorted by relevance
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32 _REG_(M33_ITM_STIM0_OFFSET) // M33_ITM_STIM039 _REG_(M33_ITM_TER0_OFFSET) // M33_ITM_TER046 _REG_(M33_ITM_TPR_OFFSET) // M33_ITM_TPR53 _REG_(M33_ITM_TCR_OFFSET) // M33_ITM_TCR69 _REG_(M33_INT_ATREADY_OFFSET) // M33_INT_ATREADY77 _REG_(M33_INT_ATVALID_OFFSET) // M33_INT_ATVALID85 _REG_(M33_ITM_ITCTRL_OFFSET) // M33_ITM_ITCTRL92 _REG_(M33_ITM_DEVARCH_OFFSET) // M33_ITM_DEVARCH103 _REG_(M33_ITM_DEVTYPE_OFFSET) // M33_ITM_DEVTYPE109 _REG_(M33_ITM_PIDR4_OFFSET) // M33_ITM_PIDR4[all …]
27 _REG_(POWMAN_BADPASSWD_OFFSET) // POWMAN_BADPASSWD32 _REG_(POWMAN_VREG_CTRL_OFFSET) // POWMAN_VREG_CTRL41 _REG_(POWMAN_VREG_STS_OFFSET) // POWMAN_VREG_STS47 _REG_(POWMAN_VREG_OFFSET) // POWMAN_VREG54 _REG_(POWMAN_VREG_LP_ENTRY_OFFSET) // POWMAN_VREG_LP_ENTRY61 _REG_(POWMAN_VREG_LP_EXIT_OFFSET) // POWMAN_VREG_LP_EXIT68 _REG_(POWMAN_BOD_CTRL_OFFSET) // POWMAN_BOD_CTRL73 _REG_(POWMAN_BOD_OFFSET) // POWMAN_BOD79 _REG_(POWMAN_BOD_LP_ENTRY_OFFSET) // POWMAN_BOD_LP_ENTRY85 _REG_(POWMAN_BOD_LP_EXIT_OFFSET) // POWMAN_BOD_LP_EXIT[all …]
27 _REG_(ACCESSCTRL_LOCK_OFFSET) // ACCESSCTRL_LOCK35 _REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) // ACCESSCTRL_FORCE_CORE_NS40 _REG_(ACCESSCTRL_CFGRESET_OFFSET) // ACCESSCTRL_CFGRESET46 _REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) // ACCESSCTRL_GPIO_NSMASK051 _REG_(ACCESSCTRL_ROM_OFFSET) // ACCESSCTRL_ROM63 _REG_(ACCESSCTRL_XIP_MAIN_OFFSET) // ACCESSCTRL_XIP_MAIN76 _REG_(ACCESSCTRL_SRAM0_OFFSET) // ACCESSCTRL_SRAM088 _REG_(ACCESSCTRL_DMA_OFFSET) // ACCESSCTRL_DMA100 _REG_(ACCESSCTRL_USBCTRL_OFFSET) // ACCESSCTRL_USBCTRL113 _REG_(ACCESSCTRL_PIO0_OFFSET) // ACCESSCTRL_PIO0[all …]
28 _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR33 _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR38 _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT44 _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG66 _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL71 _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR76 _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR81 _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG86 _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL91 _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT[all …]
29 _REG_(SIO_CPUID_OFFSET) // SIO_CPUID34 _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN39 _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN51 _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT56 _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT66 _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET71 _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET81 _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR86 _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR96 _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR[all …]
27 _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON41 _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR48 _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR55 _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD64 _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT69 _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT74 _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT79 _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT86 _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT103 _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK[all …]
28 _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP35 _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP143 _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL51 _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR56 _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD61 _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL90 _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS114 _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL119 _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS155 _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE[all …]
27 _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV33 _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL48 _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL63 _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR68 _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR73 _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL86 _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE106 _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF126 _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS148 _REG_(PIO_CTRL_OFFSET) // PIO_CTRL[all …]
28 _REG_(OTP_SW_LOCK0_OFFSET) // OTP_SW_LOCK034 _REG_(OTP_SBPI_INSTR_OFFSET) // OTP_SBPI_INSTR46 _REG_(OTP_SBPI_WDATA_0_OFFSET) // OTP_SBPI_WDATA_052 _REG_(OTP_SBPI_RDATA_0_OFFSET) // OTP_SBPI_RDATA_057 _REG_(OTP_SBPI_STATUS_OFFSET) // OTP_SBPI_STATUS65 _REG_(OTP_USR_OFFSET) // OTP_USR71 _REG_(OTP_DBG_OFFSET) // OTP_DBG83 _REG_(OTP_BIST_OFFSET) // OTP_BIST93 _REG_(OTP_CRT_KEY_W0_OFFSET) // OTP_CRT_KEY_W098 _REG_(OTP_CRITICAL_OFFSET) // OTP_CRITICAL[all …]
31 _REG_(M33_CPUID_OFFSET) // M33_CPUID40 _REG_(M33_ICSR_OFFSET) // M33_ICSR56 _REG_(M33_VTOR_OFFSET) // M33_VTOR61 _REG_(M33_AIRCR_OFFSET) // M33_AIRCR73 _REG_(M33_SCR_OFFSET) // M33_SCR81 _REG_(M33_CCR_OFFSET) // M33_CCR96 _REG_(M33_SHPR1_OFFSET) // M33_SHPR1104 _REG_(M33_SHCSR_OFFSET) // M33_SHCSR128 _REG_(M33_CFSR_OFFSET) // M33_CFSR147 _REG_(M33_HFSR_OFFSET) // M33_HFSR[all …]
117 _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL128 _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV133 _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED141 _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL148 _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS154 _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ159 _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ164 _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ169 _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY174 _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL[all …]
27 _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW32 _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW37 _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR42 _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR48 _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM053 _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED58 _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH63 _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL68 _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE74 _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE[all …]
27 _REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR36 _REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR45 _REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR54 _REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG60 _REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID67 _REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA072 _REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE78 _REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT183 _REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC90 _REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL[all …]
27 _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR38 _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV44 _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR49 _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC55 _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP62 _REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE78 _REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF94 _REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS114 _REG_(PWM_EN_OFFSET) // PWM_EN130 _REG_(PWM_INTR_OFFSET) // PWM_INTR[all …]
39 _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS46 _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL56 _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE92 _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF128 _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS166 _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS173 _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL181 _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS188 _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL200 _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE[all …]
28 _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR33 _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR38 _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT43 _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG63 _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL68 _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR73 _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR78 _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG83 _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL88 _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT[all …]
29 _REG_(SIO_CPUID_OFFSET) // SIO_CPUID34 _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN39 _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN46 _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT51 _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET56 _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR61 _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR66 _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE71 _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET76 _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR[all …]
27 _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV33 _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL48 _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL60 _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR65 _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR70 _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL83 _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE99 _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF115 _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS133 _REG_(PIO_CTRL_OFFSET) // PIO_CTRL[all …]
27 _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR042 _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR147 _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR52 _REG_(SSI_MWCR_OFFSET) // SSI_MWCR59 _REG_(SSI_SER_OFFSET) // SSI_SER64 _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR69 _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR74 _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR79 _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR84 _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR[all …]
28 _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP35 _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP143 _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL50 _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR55 _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD60 _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL88 _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS110 _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL115 _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS151 _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE[all …]
29 _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR37 _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR42 _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR47 _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB56 _REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER63 _REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER70 _REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR77 _REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR85 _REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR095 _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID[all …]
101 _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL111 _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV117 _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED125 _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL132 _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS138 _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ143 _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ148 _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ153 _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY158 _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL[all …]
27 _REG_(UART_UARTDR_OFFSET) // UART_UARTDR36 _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR46 _REG_(UART_UARTFR_OFFSET) // UART_UARTFR61 _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR66 _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD71 _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD76 _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H87 _REG_(UART_UARTCR_OFFSET) // UART_UARTCR103 _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS109 _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC[all …]
