1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_PIO_H 9 #define _HARDWARE_STRUCTS_PIO_H 10 11 /** 12 * \file rp2040/pio.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/pio.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/pio.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV 28 // Clock divisor register for state machine 0 + 29 // 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256) 30 // 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor 31 io_rw_32 clkdiv; 32 33 _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL 34 // Execution/behavioural settings for state machine 0 35 // 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,... 36 // 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is... 37 // 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,... 38 // 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN 39 // 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable 40 // 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable + 41 // 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins 42 // 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom 43 // 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address 44 // 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction 45 // 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction 46 io_rw_32 execctrl; 47 48 _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL 49 // Control behaviour of the input/output shift registers for state machine 0 50 // 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and... 51 // 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and... 52 // 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or... 53 // 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or... 54 // 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right 55 // 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left) 56 // 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i 57 // 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i 58 io_rw_32 shiftctrl; 59 60 _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR 61 // Current instruction address of state machine 0 62 // 0x0000001f [4:0] SM0_ADDR (0x00) 63 io_ro_32 addr; 64 65 _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR 66 // Read to see the instruction currently addressed by state machine 0's program counter + 67 // 0x0000ffff [15:0] SM0_INSTR (-) 68 io_rw_32 instr; 69 70 _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL 71 // State machine pin control 72 // 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction... 73 // 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET 74 // 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS... 75 // 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of... 76 // 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a... 77 // 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET... 78 // 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT... 79 io_rw_32 pinctrl; 80 } pio_sm_hw_t; 81 82 typedef struct { 83 _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE 84 // Interrupt Enable for irq0 85 // 0x00000800 [11] SM3 (0) 86 // 0x00000400 [10] SM2 (0) 87 // 0x00000200 [9] SM1 (0) 88 // 0x00000100 [8] SM0 (0) 89 // 0x00000080 [7] SM3_TXNFULL (0) 90 // 0x00000040 [6] SM2_TXNFULL (0) 91 // 0x00000020 [5] SM1_TXNFULL (0) 92 // 0x00000010 [4] SM0_TXNFULL (0) 93 // 0x00000008 [3] SM3_RXNEMPTY (0) 94 // 0x00000004 [2] SM2_RXNEMPTY (0) 95 // 0x00000002 [1] SM1_RXNEMPTY (0) 96 // 0x00000001 [0] SM0_RXNEMPTY (0) 97 io_rw_32 inte; 98 99 _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF 100 // Interrupt Force for irq0 101 // 0x00000800 [11] SM3 (0) 102 // 0x00000400 [10] SM2 (0) 103 // 0x00000200 [9] SM1 (0) 104 // 0x00000100 [8] SM0 (0) 105 // 0x00000080 [7] SM3_TXNFULL (0) 106 // 0x00000040 [6] SM2_TXNFULL (0) 107 // 0x00000020 [5] SM1_TXNFULL (0) 108 // 0x00000010 [4] SM0_TXNFULL (0) 109 // 0x00000008 [3] SM3_RXNEMPTY (0) 110 // 0x00000004 [2] SM2_RXNEMPTY (0) 111 // 0x00000002 [1] SM1_RXNEMPTY (0) 112 // 0x00000001 [0] SM0_RXNEMPTY (0) 113 io_rw_32 intf; 114 115 _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS 116 // Interrupt status after masking & forcing for irq0 117 // 0x00000800 [11] SM3 (0) 118 // 0x00000400 [10] SM2 (0) 119 // 0x00000200 [9] SM1 (0) 120 // 0x00000100 [8] SM0 (0) 121 // 0x00000080 [7] SM3_TXNFULL (0) 122 // 0x00000040 [6] SM2_TXNFULL (0) 123 // 0x00000020 [5] SM1_TXNFULL (0) 124 // 0x00000010 [4] SM0_TXNFULL (0) 125 // 0x00000008 [3] SM3_RXNEMPTY (0) 126 // 0x00000004 [2] SM2_RXNEMPTY (0) 127 // 0x00000002 [1] SM1_RXNEMPTY (0) 128 // 0x00000001 [0] SM0_RXNEMPTY (0) 129 io_ro_32 ints; 130 } pio_irq_ctrl_hw_t; 131 132 typedef struct { 133 _REG_(PIO_CTRL_OFFSET) // PIO_CTRL 134 // PIO control register 135 // 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial... 136 // 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may... 137 // 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by... 138 io_rw_32 ctrl; 139 140 _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT 141 // FIFO status register 142 // 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty 143 // 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full 144 // 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty 145 // 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full 146 io_ro_32 fstat; 147 148 _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG 149 // FIFO debug register 150 // 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a... 151 // 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i 152 // 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i 153 // 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a... 154 io_rw_32 fdebug; 155 156 _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL 157 // FIFO levels 158 // 0xf0000000 [31:28] RX3 (0x0) 159 // 0x0f000000 [27:24] TX3 (0x0) 160 // 0x00f00000 [23:20] RX2 (0x0) 161 // 0x000f0000 [19:16] TX2 (0x0) 162 // 0x0000f000 [15:12] RX1 (0x0) 163 // 0x00000f00 [11:8] TX1 (0x0) 164 // 0x000000f0 [7:4] RX0 (0x0) 165 // 0x0000000f [3:0] TX0 (0x0) 166 io_ro_32 flevel; 167 168 // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes) 169 _REG_(PIO_TXF0_OFFSET) // PIO_TXF0 170 // Direct write access to the TX FIFO for this state machine 171 // 0xffffffff [31:0] TXF0 (0x00000000) 172 io_wo_32 txf[4]; 173 174 // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes) 175 _REG_(PIO_RXF0_OFFSET) // PIO_RXF0 176 // Direct read access to the RX FIFO for this state machine 177 // 0xffffffff [31:0] RXF0 (-) 178 io_ro_32 rxf[4]; 179 180 _REG_(PIO_IRQ_OFFSET) // PIO_IRQ 181 // State machine IRQ flags register 182 // 0x000000ff [7:0] IRQ (0x00) 183 io_rw_32 irq; 184 185 _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE 186 // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ 187 // 0x000000ff [7:0] IRQ_FORCE (0x00) 188 io_wo_32 irq_force; 189 190 _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS 191 // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities 192 // 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000) 193 io_rw_32 input_sync_bypass; 194 195 _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT 196 // Read to sample the pad output values PIO is currently driving to the GPIOs 197 // 0xffffffff [31:0] DBG_PADOUT (0x00000000) 198 io_ro_32 dbg_padout; 199 200 _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE 201 // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs 202 // 0xffffffff [31:0] DBG_PADOE (0x00000000) 203 io_ro_32 dbg_padoe; 204 205 _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO 206 // The PIO hardware has some free parameters that may vary between chip products 207 // 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of... 208 // 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with 209 // 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words 210 io_ro_32 dbg_cfginfo; 211 212 // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes) 213 _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0 214 // Write-only access to instruction memory location 0 215 // 0x0000ffff [15:0] INSTR_MEM0 (0x0000) 216 io_wo_32 instr_mem[32]; 217 218 pio_sm_hw_t sm[4]; 219 220 _REG_(PIO_INTR_OFFSET) // PIO_INTR 221 // Raw Interrupts 222 // 0x00000800 [11] SM3 (0) 223 // 0x00000400 [10] SM2 (0) 224 // 0x00000200 [9] SM1 (0) 225 // 0x00000100 [8] SM0 (0) 226 // 0x00000080 [7] SM3_TXNFULL (0) 227 // 0x00000040 [6] SM2_TXNFULL (0) 228 // 0x00000020 [5] SM1_TXNFULL (0) 229 // 0x00000010 [4] SM0_TXNFULL (0) 230 // 0x00000008 [3] SM3_RXNEMPTY (0) 231 // 0x00000004 [2] SM2_RXNEMPTY (0) 232 // 0x00000002 [1] SM1_RXNEMPTY (0) 233 // 0x00000001 [0] SM0_RXNEMPTY (0) 234 io_ro_32 intr; 235 236 union { 237 struct { 238 _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE 239 // Interrupt Enable for irq0 240 // 0x00000800 [11] SM3 (0) 241 // 0x00000400 [10] SM2 (0) 242 // 0x00000200 [9] SM1 (0) 243 // 0x00000100 [8] SM0 (0) 244 // 0x00000080 [7] SM3_TXNFULL (0) 245 // 0x00000040 [6] SM2_TXNFULL (0) 246 // 0x00000020 [5] SM1_TXNFULL (0) 247 // 0x00000010 [4] SM0_TXNFULL (0) 248 // 0x00000008 [3] SM3_RXNEMPTY (0) 249 // 0x00000004 [2] SM2_RXNEMPTY (0) 250 // 0x00000002 [1] SM1_RXNEMPTY (0) 251 // 0x00000001 [0] SM0_RXNEMPTY (0) 252 io_rw_32 inte0; 253 254 _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF 255 // Interrupt Force for irq0 256 // 0x00000800 [11] SM3 (0) 257 // 0x00000400 [10] SM2 (0) 258 // 0x00000200 [9] SM1 (0) 259 // 0x00000100 [8] SM0 (0) 260 // 0x00000080 [7] SM3_TXNFULL (0) 261 // 0x00000040 [6] SM2_TXNFULL (0) 262 // 0x00000020 [5] SM1_TXNFULL (0) 263 // 0x00000010 [4] SM0_TXNFULL (0) 264 // 0x00000008 [3] SM3_RXNEMPTY (0) 265 // 0x00000004 [2] SM2_RXNEMPTY (0) 266 // 0x00000002 [1] SM1_RXNEMPTY (0) 267 // 0x00000001 [0] SM0_RXNEMPTY (0) 268 io_rw_32 intf0; 269 270 _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS 271 // Interrupt status after masking & forcing for irq0 272 // 0x00000800 [11] SM3 (0) 273 // 0x00000400 [10] SM2 (0) 274 // 0x00000200 [9] SM1 (0) 275 // 0x00000100 [8] SM0 (0) 276 // 0x00000080 [7] SM3_TXNFULL (0) 277 // 0x00000040 [6] SM2_TXNFULL (0) 278 // 0x00000020 [5] SM1_TXNFULL (0) 279 // 0x00000010 [4] SM0_TXNFULL (0) 280 // 0x00000008 [3] SM3_RXNEMPTY (0) 281 // 0x00000004 [2] SM2_RXNEMPTY (0) 282 // 0x00000002 [1] SM1_RXNEMPTY (0) 283 // 0x00000001 [0] SM0_RXNEMPTY (0) 284 io_ro_32 ints0; 285 286 _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE 287 // Interrupt Enable for irq1 288 // 0x00000800 [11] SM3 (0) 289 // 0x00000400 [10] SM2 (0) 290 // 0x00000200 [9] SM1 (0) 291 // 0x00000100 [8] SM0 (0) 292 // 0x00000080 [7] SM3_TXNFULL (0) 293 // 0x00000040 [6] SM2_TXNFULL (0) 294 // 0x00000020 [5] SM1_TXNFULL (0) 295 // 0x00000010 [4] SM0_TXNFULL (0) 296 // 0x00000008 [3] SM3_RXNEMPTY (0) 297 // 0x00000004 [2] SM2_RXNEMPTY (0) 298 // 0x00000002 [1] SM1_RXNEMPTY (0) 299 // 0x00000001 [0] SM0_RXNEMPTY (0) 300 io_rw_32 inte1; 301 302 _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF 303 // Interrupt Force for irq1 304 // 0x00000800 [11] SM3 (0) 305 // 0x00000400 [10] SM2 (0) 306 // 0x00000200 [9] SM1 (0) 307 // 0x00000100 [8] SM0 (0) 308 // 0x00000080 [7] SM3_TXNFULL (0) 309 // 0x00000040 [6] SM2_TXNFULL (0) 310 // 0x00000020 [5] SM1_TXNFULL (0) 311 // 0x00000010 [4] SM0_TXNFULL (0) 312 // 0x00000008 [3] SM3_RXNEMPTY (0) 313 // 0x00000004 [2] SM2_RXNEMPTY (0) 314 // 0x00000002 [1] SM1_RXNEMPTY (0) 315 // 0x00000001 [0] SM0_RXNEMPTY (0) 316 io_rw_32 intf1; 317 318 _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS 319 // Interrupt status after masking & forcing for irq1 320 // 0x00000800 [11] SM3 (0) 321 // 0x00000400 [10] SM2 (0) 322 // 0x00000200 [9] SM1 (0) 323 // 0x00000100 [8] SM0 (0) 324 // 0x00000080 [7] SM3_TXNFULL (0) 325 // 0x00000040 [6] SM2_TXNFULL (0) 326 // 0x00000020 [5] SM1_TXNFULL (0) 327 // 0x00000010 [4] SM0_TXNFULL (0) 328 // 0x00000008 [3] SM3_RXNEMPTY (0) 329 // 0x00000004 [2] SM2_RXNEMPTY (0) 330 // 0x00000002 [1] SM1_RXNEMPTY (0) 331 // 0x00000001 [0] SM0_RXNEMPTY (0) 332 io_ro_32 ints1; 333 }; 334 pio_irq_ctrl_hw_t irq_ctrl[2]; 335 }; 336 } pio_hw_t; 337 338 #define pio0_hw ((pio_hw_t *)PIO0_BASE) 339 #define pio1_hw ((pio_hw_t *)PIO1_BASE) 340 static_assert(sizeof (pio_hw_t) == 0x0144, ""); 341 342 #endif // _HARDWARE_STRUCTS_PIO_H 343 344
