1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_TIMER_H 9 #define _HARDWARE_STRUCTS_TIMER_H 10 11 /** 12 * \file rp2040/timer.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/timer.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/timer.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW 28 // Write to bits 63:32 of time + 29 // 0xffffffff [31:0] TIMEHW (0x00000000) 30 io_wo_32 timehw; 31 32 _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW 33 // Write to bits 31:0 of time + 34 // 0xffffffff [31:0] TIMELW (0x00000000) 35 io_wo_32 timelw; 36 37 _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR 38 // Read from bits 63:32 of time + 39 // 0xffffffff [31:0] TIMEHR (0x00000000) 40 io_ro_32 timehr; 41 42 _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR 43 // Read from bits 31:0 of time 44 // 0xffffffff [31:0] TIMELR (0x00000000) 45 io_ro_32 timelr; 46 47 // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes) 48 _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0 49 // Arm alarm 0, and configure the time it will fire 50 // 0xffffffff [31:0] ALARM0 (0x00000000) 51 io_rw_32 alarm[4]; 52 53 _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED 54 // Indicates the armed/disarmed status of each alarm 55 // 0x0000000f [3:0] ARMED (0x0) 56 io_rw_32 armed; 57 58 _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH 59 // Raw read from bits 63:32 of time (no side effects) 60 // 0xffffffff [31:0] TIMERAWH (0x00000000) 61 io_ro_32 timerawh; 62 63 _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL 64 // Raw read from bits 31:0 of time (no side effects) 65 // 0xffffffff [31:0] TIMERAWL (0x00000000) 66 io_ro_32 timerawl; 67 68 _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE 69 // Set bits high to enable pause when the corresponding debug ports are active 70 // 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode 71 // 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode 72 io_rw_32 dbgpause; 73 74 _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE 75 // Set high to pause the timer 76 // 0x00000001 [0] PAUSE (0) 77 io_rw_32 pause; 78 79 _REG_(TIMER_INTR_OFFSET) // TIMER_INTR 80 // Raw Interrupts 81 // 0x00000008 [3] ALARM_3 (0) 82 // 0x00000004 [2] ALARM_2 (0) 83 // 0x00000002 [1] ALARM_1 (0) 84 // 0x00000001 [0] ALARM_0 (0) 85 io_rw_32 intr; 86 87 _REG_(TIMER_INTE_OFFSET) // TIMER_INTE 88 // Interrupt Enable 89 // 0x00000008 [3] ALARM_3 (0) 90 // 0x00000004 [2] ALARM_2 (0) 91 // 0x00000002 [1] ALARM_1 (0) 92 // 0x00000001 [0] ALARM_0 (0) 93 io_rw_32 inte; 94 95 _REG_(TIMER_INTF_OFFSET) // TIMER_INTF 96 // Interrupt Force 97 // 0x00000008 [3] ALARM_3 (0) 98 // 0x00000004 [2] ALARM_2 (0) 99 // 0x00000002 [1] ALARM_1 (0) 100 // 0x00000001 [0] ALARM_0 (0) 101 io_rw_32 intf; 102 103 _REG_(TIMER_INTS_OFFSET) // TIMER_INTS 104 // Interrupt status after masking & forcing 105 // 0x00000008 [3] ALARM_3 (0) 106 // 0x00000004 [2] ALARM_2 (0) 107 // 0x00000002 [1] ALARM_1 (0) 108 // 0x00000001 [0] ALARM_0 (0) 109 io_ro_32 ints; 110 } timer_hw_t; 111 112 #define timer_hw ((timer_hw_t *)TIMER_BASE) 113 static_assert(sizeof (timer_hw_t) == 0x0044, ""); 114 115 #endif // _HARDWARE_STRUCTS_TIMER_H 116 117
