1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 #ifndef _HARDWARE_STRUCTS_IO_QSPI_H
9 #define _HARDWARE_STRUCTS_IO_QSPI_H
10 
11 /**
12  * \file rp2350/io_qspi.h
13  */
14 
15 #include "hardware/address_mapped.h"
16 #include "hardware/regs/io_qspi.h"
17 
18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi
19 //
20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21 // _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
22 //
23 // Bit-field descriptions are of the form:
24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25 
26 /**
27  * \brief QSPI pin function selectors on RP2350 (used as typedef \ref gpio_function1_t)
28  */
29 typedef enum gpio_function1_rp2350 {
30     GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function
31     GPIO_FUNC1_UART = 2, ///< Select UART as QSPI pin function
32     GPIO_FUNC1_I2C = 3, ///< Select I2C as QSPI pin function
33     GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function
34     GPIO_FUNC1_UART_AUX = 11, ///< Select UART_AUX as QSPI pin function
35     GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function
36 } gpio_function1_t;
37 
38 typedef struct {
39     _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
40     // 0x04000000 [26]    IRQTOPROC    (0) interrupt to processors, after override is applied
41     // 0x00020000 [17]    INFROMPAD    (0) input signal from pad, before filtering and override are applied
42     // 0x00002000 [13]    OETOPAD      (0) output enable to pad after register override is applied
43     // 0x00000200 [9]     OUTTOPAD     (0) output signal to pad after register override is applied
44     io_ro_32 status;
45 
46     _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
47     // 0x30000000 [29:28] IRQOVER      (0x0)
48     // 0x00030000 [17:16] INOVER       (0x0)
49     // 0x0000c000 [15:14] OEOVER       (0x0)
50     // 0x00003000 [13:12] OUTOVER      (0x0)
51     // 0x0000001f [4:0]   FUNCSEL      (0x1f) 0-31 -> selects pin function according to the gpio table +
52     io_rw_32 ctrl;
53 } io_qspi_status_ctrl_hw_t;
54 
55 typedef struct {
56     _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
57     // Interrupt Enable for proc0
58     // 0x80000000 [31]    GPIO_QSPI_SD3_EDGE_HIGH (0)
59     // 0x40000000 [30]    GPIO_QSPI_SD3_EDGE_LOW (0)
60     // 0x20000000 [29]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
61     // 0x10000000 [28]    GPIO_QSPI_SD3_LEVEL_LOW (0)
62     // 0x08000000 [27]    GPIO_QSPI_SD2_EDGE_HIGH (0)
63     // 0x04000000 [26]    GPIO_QSPI_SD2_EDGE_LOW (0)
64     // 0x02000000 [25]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
65     // 0x01000000 [24]    GPIO_QSPI_SD2_LEVEL_LOW (0)
66     // 0x00800000 [23]    GPIO_QSPI_SD1_EDGE_HIGH (0)
67     // 0x00400000 [22]    GPIO_QSPI_SD1_EDGE_LOW (0)
68     // 0x00200000 [21]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
69     // 0x00100000 [20]    GPIO_QSPI_SD1_LEVEL_LOW (0)
70     // 0x00080000 [19]    GPIO_QSPI_SD0_EDGE_HIGH (0)
71     // 0x00040000 [18]    GPIO_QSPI_SD0_EDGE_LOW (0)
72     // 0x00020000 [17]    GPIO_QSPI_SD0_LEVEL_HIGH (0)
73     // 0x00010000 [16]    GPIO_QSPI_SD0_LEVEL_LOW (0)
74     // 0x00008000 [15]    GPIO_QSPI_SS_EDGE_HIGH (0)
75     // 0x00004000 [14]    GPIO_QSPI_SS_EDGE_LOW (0)
76     // 0x00002000 [13]    GPIO_QSPI_SS_LEVEL_HIGH (0)
77     // 0x00001000 [12]    GPIO_QSPI_SS_LEVEL_LOW (0)
78     // 0x00000800 [11]    GPIO_QSPI_SCLK_EDGE_HIGH (0)
79     // 0x00000400 [10]    GPIO_QSPI_SCLK_EDGE_LOW (0)
80     // 0x00000200 [9]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
81     // 0x00000100 [8]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
82     // 0x00000080 [7]     USBPHY_DM_EDGE_HIGH (0)
83     // 0x00000040 [6]     USBPHY_DM_EDGE_LOW (0)
84     // 0x00000020 [5]     USBPHY_DM_LEVEL_HIGH (0)
85     // 0x00000010 [4]     USBPHY_DM_LEVEL_LOW (0)
86     // 0x00000008 [3]     USBPHY_DP_EDGE_HIGH (0)
87     // 0x00000004 [2]     USBPHY_DP_EDGE_LOW (0)
88     // 0x00000002 [1]     USBPHY_DP_LEVEL_HIGH (0)
89     // 0x00000001 [0]     USBPHY_DP_LEVEL_LOW (0)
90     io_rw_32 inte;
91 
92     _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
93     // Interrupt Force for proc0
94     // 0x80000000 [31]    GPIO_QSPI_SD3_EDGE_HIGH (0)
95     // 0x40000000 [30]    GPIO_QSPI_SD3_EDGE_LOW (0)
96     // 0x20000000 [29]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
97     // 0x10000000 [28]    GPIO_QSPI_SD3_LEVEL_LOW (0)
98     // 0x08000000 [27]    GPIO_QSPI_SD2_EDGE_HIGH (0)
99     // 0x04000000 [26]    GPIO_QSPI_SD2_EDGE_LOW (0)
100     // 0x02000000 [25]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
101     // 0x01000000 [24]    GPIO_QSPI_SD2_LEVEL_LOW (0)
102     // 0x00800000 [23]    GPIO_QSPI_SD1_EDGE_HIGH (0)
103     // 0x00400000 [22]    GPIO_QSPI_SD1_EDGE_LOW (0)
104     // 0x00200000 [21]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
105     // 0x00100000 [20]    GPIO_QSPI_SD1_LEVEL_LOW (0)
106     // 0x00080000 [19]    GPIO_QSPI_SD0_EDGE_HIGH (0)
107     // 0x00040000 [18]    GPIO_QSPI_SD0_EDGE_LOW (0)
108     // 0x00020000 [17]    GPIO_QSPI_SD0_LEVEL_HIGH (0)
109     // 0x00010000 [16]    GPIO_QSPI_SD0_LEVEL_LOW (0)
110     // 0x00008000 [15]    GPIO_QSPI_SS_EDGE_HIGH (0)
111     // 0x00004000 [14]    GPIO_QSPI_SS_EDGE_LOW (0)
112     // 0x00002000 [13]    GPIO_QSPI_SS_LEVEL_HIGH (0)
113     // 0x00001000 [12]    GPIO_QSPI_SS_LEVEL_LOW (0)
114     // 0x00000800 [11]    GPIO_QSPI_SCLK_EDGE_HIGH (0)
115     // 0x00000400 [10]    GPIO_QSPI_SCLK_EDGE_LOW (0)
116     // 0x00000200 [9]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
117     // 0x00000100 [8]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
118     // 0x00000080 [7]     USBPHY_DM_EDGE_HIGH (0)
119     // 0x00000040 [6]     USBPHY_DM_EDGE_LOW (0)
120     // 0x00000020 [5]     USBPHY_DM_LEVEL_HIGH (0)
121     // 0x00000010 [4]     USBPHY_DM_LEVEL_LOW (0)
122     // 0x00000008 [3]     USBPHY_DP_EDGE_HIGH (0)
123     // 0x00000004 [2]     USBPHY_DP_EDGE_LOW (0)
124     // 0x00000002 [1]     USBPHY_DP_LEVEL_HIGH (0)
125     // 0x00000001 [0]     USBPHY_DP_LEVEL_LOW (0)
126     io_rw_32 intf;
127 
128     _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
129     // Interrupt status after masking & forcing for proc0
130     // 0x80000000 [31]    GPIO_QSPI_SD3_EDGE_HIGH (0)
131     // 0x40000000 [30]    GPIO_QSPI_SD3_EDGE_LOW (0)
132     // 0x20000000 [29]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
133     // 0x10000000 [28]    GPIO_QSPI_SD3_LEVEL_LOW (0)
134     // 0x08000000 [27]    GPIO_QSPI_SD2_EDGE_HIGH (0)
135     // 0x04000000 [26]    GPIO_QSPI_SD2_EDGE_LOW (0)
136     // 0x02000000 [25]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
137     // 0x01000000 [24]    GPIO_QSPI_SD2_LEVEL_LOW (0)
138     // 0x00800000 [23]    GPIO_QSPI_SD1_EDGE_HIGH (0)
139     // 0x00400000 [22]    GPIO_QSPI_SD1_EDGE_LOW (0)
140     // 0x00200000 [21]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
141     // 0x00100000 [20]    GPIO_QSPI_SD1_LEVEL_LOW (0)
142     // 0x00080000 [19]    GPIO_QSPI_SD0_EDGE_HIGH (0)
143     // 0x00040000 [18]    GPIO_QSPI_SD0_EDGE_LOW (0)
144     // 0x00020000 [17]    GPIO_QSPI_SD0_LEVEL_HIGH (0)
145     // 0x00010000 [16]    GPIO_QSPI_SD0_LEVEL_LOW (0)
146     // 0x00008000 [15]    GPIO_QSPI_SS_EDGE_HIGH (0)
147     // 0x00004000 [14]    GPIO_QSPI_SS_EDGE_LOW (0)
148     // 0x00002000 [13]    GPIO_QSPI_SS_LEVEL_HIGH (0)
149     // 0x00001000 [12]    GPIO_QSPI_SS_LEVEL_LOW (0)
150     // 0x00000800 [11]    GPIO_QSPI_SCLK_EDGE_HIGH (0)
151     // 0x00000400 [10]    GPIO_QSPI_SCLK_EDGE_LOW (0)
152     // 0x00000200 [9]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
153     // 0x00000100 [8]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
154     // 0x00000080 [7]     USBPHY_DM_EDGE_HIGH (0)
155     // 0x00000040 [6]     USBPHY_DM_EDGE_LOW (0)
156     // 0x00000020 [5]     USBPHY_DM_LEVEL_HIGH (0)
157     // 0x00000010 [4]     USBPHY_DM_LEVEL_LOW (0)
158     // 0x00000008 [3]     USBPHY_DP_EDGE_HIGH (0)
159     // 0x00000004 [2]     USBPHY_DP_EDGE_LOW (0)
160     // 0x00000002 [1]     USBPHY_DP_LEVEL_HIGH (0)
161     // 0x00000001 [0]     USBPHY_DP_LEVEL_LOW (0)
162     io_ro_32 ints;
163 } io_qspi_irq_ctrl_hw_t;
164 
165 typedef struct {
166     _REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS
167     // 0x04000000 [26]    IRQTOPROC    (0) interrupt to processors, after override is applied
168     // 0x00020000 [17]    INFROMPAD    (0) input signal from pad, before filtering and override are applied
169     // 0x00002000 [13]    OETOPAD      (0) output enable to pad after register override is applied
170     // 0x00000200 [9]     OUTTOPAD     (0) output signal to pad after register override is applied
171     io_ro_32 usbphy_dp_status;
172 
173     _REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL
174     // 0x30000000 [29:28] IRQOVER      (0x0)
175     // 0x00030000 [17:16] INOVER       (0x0)
176     // 0x0000c000 [15:14] OEOVER       (0x0)
177     // 0x00003000 [13:12] OUTOVER      (0x0)
178     // 0x0000001f [4:0]   FUNCSEL      (0x1f) 0-31 -> selects pin function according to the gpio table +
179     io_rw_32 usbphy_dp_ctrl;
180 
181     _REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS
182     // 0x04000000 [26]    IRQTOPROC    (0) interrupt to processors, after override is applied
183     // 0x00020000 [17]    INFROMPAD    (0) input signal from pad, before filtering and override are applied
184     // 0x00002000 [13]    OETOPAD      (0) output enable to pad after register override is applied
185     // 0x00000200 [9]     OUTTOPAD     (0) output signal to pad after register override is applied
186     io_ro_32 usbphy_dm_status;
187 
188     _REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL
189     // 0x30000000 [29:28] IRQOVER      (0x0)
190     // 0x00030000 [17:16] INOVER       (0x0)
191     // 0x0000c000 [15:14] OEOVER       (0x0)
192     // 0x00003000 [13:12] OUTOVER      (0x0)
193     // 0x0000001f [4:0]   FUNCSEL      (0x1f) 0-31 -> selects pin function according to the gpio table +
194     io_rw_32 usbphy_dm_ctrl;
195 
196     io_qspi_status_ctrl_hw_t io[6];
197 
198     uint32_t _pad0[112];
199 
200     _REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE
201     // 0x00000080 [7]     GPIO_QSPI_SD3 (0)
202     // 0x00000040 [6]     GPIO_QSPI_SD2 (0)
203     // 0x00000020 [5]     GPIO_QSPI_SD1 (0)
204     // 0x00000010 [4]     GPIO_QSPI_SD0 (0)
205     // 0x00000008 [3]     GPIO_QSPI_SS (0)
206     // 0x00000004 [2]     GPIO_QSPI_SCLK (0)
207     // 0x00000002 [1]     USBPHY_DM    (0)
208     // 0x00000001 [0]     USBPHY_DP    (0)
209     io_ro_32 irqsummary_proc0_secure;
210 
211     _REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE
212     // 0x00000080 [7]     GPIO_QSPI_SD3 (0)
213     // 0x00000040 [6]     GPIO_QSPI_SD2 (0)
214     // 0x00000020 [5]     GPIO_QSPI_SD1 (0)
215     // 0x00000010 [4]     GPIO_QSPI_SD0 (0)
216     // 0x00000008 [3]     GPIO_QSPI_SS (0)
217     // 0x00000004 [2]     GPIO_QSPI_SCLK (0)
218     // 0x00000002 [1]     USBPHY_DM    (0)
219     // 0x00000001 [0]     USBPHY_DP    (0)
220     io_ro_32 irqsummary_proc0_nonsecure;
221 
222     _REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE
223     // 0x00000080 [7]     GPIO_QSPI_SD3 (0)
224     // 0x00000040 [6]     GPIO_QSPI_SD2 (0)
225     // 0x00000020 [5]     GPIO_QSPI_SD1 (0)
226     // 0x00000010 [4]     GPIO_QSPI_SD0 (0)
227     // 0x00000008 [3]     GPIO_QSPI_SS (0)
228     // 0x00000004 [2]     GPIO_QSPI_SCLK (0)
229     // 0x00000002 [1]     USBPHY_DM    (0)
230     // 0x00000001 [0]     USBPHY_DP    (0)
231     io_ro_32 irqsummary_proc1_secure;
232 
233     _REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE
234     // 0x00000080 [7]     GPIO_QSPI_SD3 (0)
235     // 0x00000040 [6]     GPIO_QSPI_SD2 (0)
236     // 0x00000020 [5]     GPIO_QSPI_SD1 (0)
237     // 0x00000010 [4]     GPIO_QSPI_SD0 (0)
238     // 0x00000008 [3]     GPIO_QSPI_SS (0)
239     // 0x00000004 [2]     GPIO_QSPI_SCLK (0)
240     // 0x00000002 [1]     USBPHY_DM    (0)
241     // 0x00000001 [0]     USBPHY_DP    (0)
242     io_ro_32 irqsummary_proc1_nonsecure;
243 
244     _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE
245     // 0x00000080 [7]     GPIO_QSPI_SD3 (0)
246     // 0x00000040 [6]     GPIO_QSPI_SD2 (0)
247     // 0x00000020 [5]     GPIO_QSPI_SD1 (0)
248     // 0x00000010 [4]     GPIO_QSPI_SD0 (0)
249     // 0x00000008 [3]     GPIO_QSPI_SS (0)
250     // 0x00000004 [2]     GPIO_QSPI_SCLK (0)
251     // 0x00000002 [1]     USBPHY_DM    (0)
252     // 0x00000001 [0]     USBPHY_DP    (0)
253     io_ro_32 irqsummary_dormant_wake_secure;
254 
255     _REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE
256     // 0x00000080 [7]     GPIO_QSPI_SD3 (0)
257     // 0x00000040 [6]     GPIO_QSPI_SD2 (0)
258     // 0x00000020 [5]     GPIO_QSPI_SD1 (0)
259     // 0x00000010 [4]     GPIO_QSPI_SD0 (0)
260     // 0x00000008 [3]     GPIO_QSPI_SS (0)
261     // 0x00000004 [2]     GPIO_QSPI_SCLK (0)
262     // 0x00000002 [1]     USBPHY_DM    (0)
263     // 0x00000001 [0]     USBPHY_DP    (0)
264     io_ro_32 irqsummary_dormant_wake_nonsecure;
265 
266     _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
267     // Raw Interrupts
268     // 0x80000000 [31]    GPIO_QSPI_SD3_EDGE_HIGH (0)
269     // 0x40000000 [30]    GPIO_QSPI_SD3_EDGE_LOW (0)
270     // 0x20000000 [29]    GPIO_QSPI_SD3_LEVEL_HIGH (0)
271     // 0x10000000 [28]    GPIO_QSPI_SD3_LEVEL_LOW (0)
272     // 0x08000000 [27]    GPIO_QSPI_SD2_EDGE_HIGH (0)
273     // 0x04000000 [26]    GPIO_QSPI_SD2_EDGE_LOW (0)
274     // 0x02000000 [25]    GPIO_QSPI_SD2_LEVEL_HIGH (0)
275     // 0x01000000 [24]    GPIO_QSPI_SD2_LEVEL_LOW (0)
276     // 0x00800000 [23]    GPIO_QSPI_SD1_EDGE_HIGH (0)
277     // 0x00400000 [22]    GPIO_QSPI_SD1_EDGE_LOW (0)
278     // 0x00200000 [21]    GPIO_QSPI_SD1_LEVEL_HIGH (0)
279     // 0x00100000 [20]    GPIO_QSPI_SD1_LEVEL_LOW (0)
280     // 0x00080000 [19]    GPIO_QSPI_SD0_EDGE_HIGH (0)
281     // 0x00040000 [18]    GPIO_QSPI_SD0_EDGE_LOW (0)
282     // 0x00020000 [17]    GPIO_QSPI_SD0_LEVEL_HIGH (0)
283     // 0x00010000 [16]    GPIO_QSPI_SD0_LEVEL_LOW (0)
284     // 0x00008000 [15]    GPIO_QSPI_SS_EDGE_HIGH (0)
285     // 0x00004000 [14]    GPIO_QSPI_SS_EDGE_LOW (0)
286     // 0x00002000 [13]    GPIO_QSPI_SS_LEVEL_HIGH (0)
287     // 0x00001000 [12]    GPIO_QSPI_SS_LEVEL_LOW (0)
288     // 0x00000800 [11]    GPIO_QSPI_SCLK_EDGE_HIGH (0)
289     // 0x00000400 [10]    GPIO_QSPI_SCLK_EDGE_LOW (0)
290     // 0x00000200 [9]     GPIO_QSPI_SCLK_LEVEL_HIGH (0)
291     // 0x00000100 [8]     GPIO_QSPI_SCLK_LEVEL_LOW (0)
292     // 0x00000080 [7]     USBPHY_DM_EDGE_HIGH (0)
293     // 0x00000040 [6]     USBPHY_DM_EDGE_LOW (0)
294     // 0x00000020 [5]     USBPHY_DM_LEVEL_HIGH (0)
295     // 0x00000010 [4]     USBPHY_DM_LEVEL_LOW (0)
296     // 0x00000008 [3]     USBPHY_DP_EDGE_HIGH (0)
297     // 0x00000004 [2]     USBPHY_DP_EDGE_LOW (0)
298     // 0x00000002 [1]     USBPHY_DP_LEVEL_HIGH (0)
299     // 0x00000001 [0]     USBPHY_DP_LEVEL_LOW (0)
300     io_rw_32 intr;
301 
302     union {
303         struct {
304             io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
305             io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
306             io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
307         };
308         io_qspi_irq_ctrl_hw_t irq_ctrl[3];
309     };
310 } io_qspi_hw_t;
311 
312 #define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
313 static_assert(sizeof (io_qspi_hw_t) == 0x0240, "");
314 
315 #endif // _HARDWARE_STRUCTS_IO_QSPI_H
316 
317