1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_SCB_H 9 #define _HARDWARE_STRUCTS_SCB_H 10 11 /** 12 * \file rp2350/scb.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/m33.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/m33.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 #if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV 27 #error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1" 28 #endif 29 30 typedef struct { 31 _REG_(M33_CPUID_OFFSET) // M33_CPUID 32 // Provides identification information for the PE, including an implementer code for the device and... 33 // 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been... 34 // 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number 35 // 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE 36 // 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device 37 // 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device 38 io_ro_32 cpuid; 39 40 _REG_(M33_ICSR_OFFSET) // M33_ICSR 41 // Controls and provides status information for NMI, PendSV, SysTick and interrupts 42 // 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending 43 // 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared 44 // 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending 45 // 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS 46 // 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending 47 // 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS 48 // 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the... 49 // 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced... 50 // 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by... 51 // 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and... 52 // 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than... 53 // 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception 54 io_rw_32 icsr; 55 56 _REG_(M33_VTOR_OFFSET) // M33_VTOR 57 // Vector Table Offset Register 58 // 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field 59 io_rw_32 vtor; 60 61 _REG_(M33_AIRCR_OFFSET) // M33_AIRCR 62 // Application Interrupt and Reset Control Register 63 // 0xffff0000 [31:16] VECTKEY (0x0000) Register key: + 64 // 0x00008000 [15] ENDIANESS (0) Data endianness implemented: + 65 // 0x00004000 [14] PRIS (0) Prioritize Secure exceptions 66 // 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable 67 // 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field 68 // 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only 69 // 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to... 70 // 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and... 71 io_rw_32 aircr; 72 73 _REG_(M33_SCR_OFFSET) // M33_SCR 74 // System Control Register 75 // 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: + 76 // 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states + 77 // 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep... 78 // 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode... 79 io_rw_32 scr; 80 81 _REG_(M33_CCR_OFFSET) // M33_CCR 82 // Sets or returns configuration and control data 83 // 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS 84 // 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in... 85 // 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS 86 // 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while... 87 // 0x00000200 [9] RES1 (1) Reserved, RES1 88 // 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers... 89 // 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when... 90 // 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses 91 // 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted... 92 // 0x00000001 [0] RES1_1 (1) Reserved, RES1 93 io_rw_32 ccr; 94 95 // (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes) 96 _REG_(M33_SHPR1_OFFSET) // M33_SHPR1 97 // Sets or returns priority for system handlers 4 - 7 98 // 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault 99 // 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault 100 // 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault 101 // 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault 102 io_rw_32 shpr[3]; 103 104 _REG_(M33_SHCSR_OFFSET) // M33_SHCSR 105 // Provides access to the active and pending status of system exceptions 106 // 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS 107 // 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception 108 // 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled 109 // 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS 110 // 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled 111 // 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS 112 // 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS 113 // 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception 114 // 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS 115 // 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security... 116 // 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS 117 // 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS 118 // 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception 119 // 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS 120 // 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception 121 // 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception 122 // 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS 123 // 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active... 124 // 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception 125 // 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS 126 io_rw_32 shcsr; 127 128 _REG_(M33_CFSR_OFFSET) // M33_CFSR 129 // Contains the three Configurable Fault Status Registers 130 // 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by... 131 // 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error... 132 // 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error... 133 // 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or... 134 // 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error... 135 // 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR 136 // 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction... 137 // 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register 138 // 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state... 139 // 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during... 140 // 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during... 141 // 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred 142 // 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred 143 // 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch... 144 // 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions 145 io_rw_32 cfsr; 146 147 _REG_(M33_HFSR_OFFSET) // M33_HFSR 148 // Shows the cause of any HardFaults 149 // 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred 150 // 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has... 151 // 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector... 152 io_rw_32 hfsr; 153 154 _REG_(M33_DFSR_OFFSET) // M33_DFSR 155 // Shows which debug event occurred 156 // 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request... 157 // 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug... 158 // 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event... 159 // 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event... 160 // 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event... 161 io_rw_32 dfsr; 162 163 _REG_(M33_MMFAR_OFFSET) // M33_MMFAR 164 // Shows the address of the memory location that caused an MPU fault 165 // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... 166 io_rw_32 mmfar; 167 168 _REG_(M33_BFAR_OFFSET) // M33_BFAR 169 // Shows the address associated with a precise data access BusFault 170 // 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location... 171 io_rw_32 bfar; 172 173 uint32_t _pad0; 174 175 // (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes) 176 _REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0 177 // Gives top-level information about the instruction set supported by the PE 178 // 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support 179 // 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support 180 io_ro_32 id_pfr[2]; 181 182 _REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0 183 // Provides top level information about the debug system 184 // 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture 185 io_ro_32 id_dfr0; 186 187 _REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0 188 // Provides information about the IMPLEMENTATION DEFINED features of the PE 189 // 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning 190 // 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning 191 // 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning 192 // 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning 193 io_ro_32 id_afr0; 194 195 // (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes) 196 _REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0 197 // Provides information about the implemented memory model and memory management support 198 // 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers 199 // 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs) 200 // 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented 201 // 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented 202 // 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system... 203 io_ro_32 id_mmfr[4]; 204 205 // (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes) 206 _REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0 207 // Provides information about the instruction set implemented by the PE 208 // 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions 209 // 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions 210 // 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions 211 // 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions 212 // 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions 213 // 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions 214 io_ro_32 id_isar[6]; 215 216 uint32_t _pad1; 217 218 _REG_(M33_CTR_OFFSET) // M33_CTR 219 // Provides information about the architecture of the caches 220 // 0x80000000 [31] RES1 (1) Reserved, RES1 221 // 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of... 222 // 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the... 223 // 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line... 224 // 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1 225 // 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line... 226 io_ro_32 ctr; 227 228 uint32_t _pad2[2]; 229 230 _REG_(M33_CPACR_OFFSET) // M33_CPACR 231 // Specifies the access privileges for coprocessors and the FP Extension 232 // 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored 233 // 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality 234 // 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7 235 // 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6 236 // 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5 237 // 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4 238 // 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3 239 // 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2 240 // 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1 241 // 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0 242 io_rw_32 cpacr; 243 244 _REG_(M33_NSACR_OFFSET) // M33_NSACR 245 // Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 246 // 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension 247 // 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension 248 // 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7 249 // 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6 250 // 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5 251 // 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4 252 // 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3 253 // 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2 254 // 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1 255 // 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0 256 io_rw_32 nsacr; 257 } armv8m_scb_hw_t; 258 259 #define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET)) 260 #define scb_ns_hw ((armv8m_scb_hw_t *)(PPB_NONSEC_BASE + M33_CPUID_OFFSET)) 261 static_assert(sizeof (armv8m_scb_hw_t) == 0x0090, ""); 262 263 #endif // _HARDWARE_STRUCTS_SCB_H 264 265
