1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_I2C_H 9 #define _HARDWARE_STRUCTS_I2C_H 10 11 /** 12 * \file rp2350/i2c.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/i2c.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_i2c 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/i2c.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON 28 // I2C Control Register 29 // 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of... 30 // 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus... 31 // 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY... 32 // 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt... 33 // 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,... 34 // 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when... 35 // 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in... 36 // 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the... 37 // 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c... 38 // 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled 39 io_rw_32 con; 40 41 _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR 42 // I2C Target Address Register 43 // 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID... 44 // 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is... 45 // 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction 46 io_rw_32 tar; 47 48 _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR 49 // I2C Slave Address Register 50 // 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is... 51 io_rw_32 sar; 52 53 uint32_t _pad0; 54 55 _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD 56 // I2C Rx/Tx Data Buffer and Command Register 57 // 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address... 58 // 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the... 59 // 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the... 60 // 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed 61 // 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or... 62 io_rw_32 data_cmd; 63 64 _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT 65 // Standard Speed I2C Clock SCL High Count Register 66 // 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction... 67 io_rw_32 ss_scl_hcnt; 68 69 _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT 70 // Standard Speed I2C Clock SCL Low Count Register 71 // 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction... 72 io_rw_32 ss_scl_lcnt; 73 74 _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT 75 // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register 76 // 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction... 77 io_rw_32 fs_scl_hcnt; 78 79 _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT 80 // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register 81 // 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction... 82 io_rw_32 fs_scl_lcnt; 83 84 uint32_t _pad1[2]; 85 86 _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT 87 // I2C Interrupt Status Register 88 // 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of... 89 // 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit 90 // 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of... 91 // 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit 92 // 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit 93 // 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit 94 // 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit 95 // 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit 96 // 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit 97 // 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit 98 // 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit 99 // 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit 100 // 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit 101 io_ro_32 intr_stat; 102 103 _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK 104 // I2C Interrupt Mask Register 105 // 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in... 106 // 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register 107 // 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register 108 // 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register 109 // 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register 110 // 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register 111 // 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register 112 // 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register 113 // 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register 114 // 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register 115 // 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register 116 // 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register 117 // 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register 118 io_rw_32 intr_mask; 119 120 _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT 121 // I2C Raw Interrupt Status Register 122 // 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on... 123 // 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it... 124 // 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has... 125 // 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the... 126 // 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set... 127 // 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,... 128 // 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,... 129 // 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a... 130 // 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs... 131 // 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to... 132 // 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the... 133 // 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to... 134 // 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer... 135 io_ro_32 raw_intr_stat; 136 137 _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL 138 // I2C Receive FIFO Threshold Register 139 // 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level 140 io_rw_32 rx_tl; 141 142 _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL 143 // I2C Transmit FIFO Threshold Register 144 // 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level 145 io_rw_32 tx_tl; 146 147 _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR 148 // Clear Combined and Individual Interrupt Register 149 // 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all... 150 io_ro_32 clr_intr; 151 152 _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER 153 // Clear RX_UNDER Interrupt Register 154 // 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit... 155 io_ro_32 clr_rx_under; 156 157 _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER 158 // Clear RX_OVER Interrupt Register 159 // 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit... 160 io_ro_32 clr_rx_over; 161 162 _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER 163 // Clear TX_OVER Interrupt Register 164 // 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit... 165 io_ro_32 clr_tx_over; 166 167 _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ 168 // Clear RD_REQ Interrupt Register 169 // 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)... 170 io_ro_32 clr_rd_req; 171 172 _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT 173 // Clear TX_ABRT Interrupt Register 174 // 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit... 175 io_ro_32 clr_tx_abrt; 176 177 _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE 178 // Clear RX_DONE Interrupt Register 179 // 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit... 180 io_ro_32 clr_rx_done; 181 182 _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY 183 // Clear ACTIVITY Interrupt Register 184 // 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if... 185 io_ro_32 clr_activity; 186 187 _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET 188 // Clear STOP_DET Interrupt Register 189 // 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit... 190 io_ro_32 clr_stop_det; 191 192 _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET 193 // Clear START_DET Interrupt Register 194 // 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit... 195 io_ro_32 clr_start_det; 196 197 _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL 198 // Clear GEN_CALL Interrupt Register 199 // 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit... 200 io_ro_32 clr_gen_call; 201 202 _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE 203 // I2C ENABLE Register 204 // 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data... 205 // 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort 206 // 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled 207 io_rw_32 enable; 208 209 _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS 210 // I2C STATUS Register 211 // 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status 212 // 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status 213 // 0x00000010 [4] RFF (0) Receive FIFO Completely Full 214 // 0x00000008 [3] RFNE (0) Receive FIFO Not Empty 215 // 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty 216 // 0x00000002 [1] TFNF (1) Transmit FIFO Not Full 217 // 0x00000001 [0] ACTIVITY (0) I2C Activity Status 218 io_ro_32 status; 219 220 _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR 221 // I2C Transmit FIFO Level Register 222 // 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level 223 io_ro_32 txflr; 224 225 _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR 226 // I2C Receive FIFO Level Register 227 // 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level 228 io_ro_32 rxflr; 229 230 _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD 231 // I2C SDA Hold Time Length Register 232 // 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk... 233 // 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk... 234 io_rw_32 sda_hold; 235 236 _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE 237 // I2C Transmit Abort Source Register 238 // 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands... 239 // 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit 240 // 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode... 241 // 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while... 242 // 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read... 243 // 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost... 244 // 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a... 245 // 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled... 246 // 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT... 247 // 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled... 248 // 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START... 249 // 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed... 250 // 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode... 251 // 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has... 252 // 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit 253 // 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit... 254 // 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit... 255 // 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit... 256 io_ro_32 tx_abrt_source; 257 258 _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY 259 // Generate Slave Data NACK Register 260 // 0x00000001 [0] NACK (0) Generate NACK 261 io_rw_32 slv_data_nack_only; 262 263 _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR 264 // DMA Control Register 265 // 0x00000002 [1] TDMAE (0) Transmit DMA Enable 266 // 0x00000001 [0] RDMAE (0) Receive DMA Enable 267 io_rw_32 dma_cr; 268 269 _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR 270 // DMA Transmit Data Level Register 271 // 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level 272 io_rw_32 dma_tdlr; 273 274 _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR 275 // DMA Transmit Data Level Register 276 // 0x0000000f [3:0] DMARDL (0x0) Receive Data Level 277 io_rw_32 dma_rdlr; 278 279 _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP 280 // I2C SDA Setup Register 281 // 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup 282 io_rw_32 sda_setup; 283 284 _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL 285 // I2C ACK General Call Register 286 // 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call 287 io_rw_32 ack_general_call; 288 289 _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS 290 // I2C Enable Status Register 291 // 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost 292 // 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive) 293 // 0x00000001 [0] IC_EN (0) ic_en Status 294 io_ro_32 enable_status; 295 296 _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN 297 // I2C SS, FS or FM+ spike suppression limit 298 // 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction... 299 io_rw_32 fs_spklen; 300 301 uint32_t _pad2; 302 303 _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET 304 // Clear RESTART_DET Interrupt Register 305 // 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt... 306 io_ro_32 clr_restart_det; 307 308 uint32_t _pad3[18]; 309 310 _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1 311 // Component Parameter Register 1 312 // 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16 313 // 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16 314 // 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible 315 // 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled 316 // 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs 317 // 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode 318 // 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE 319 // 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits 320 io_ro_32 comp_param_1; 321 322 _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION 323 // I2C Component Version Register 324 // 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a) 325 io_ro_32 comp_version; 326 327 _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE 328 // I2C Component Type Register 329 // 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40 330 io_ro_32 comp_type; 331 } i2c_hw_t; 332 333 #define i2c0_hw ((i2c_hw_t *)I2C0_BASE) 334 #define i2c1_hw ((i2c_hw_t *)I2C1_BASE) 335 static_assert(sizeof (i2c_hw_t) == 0x0100, ""); 336 337 #endif // _HARDWARE_STRUCTS_I2C_H 338 339
