1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_OTP_H 9 #define _HARDWARE_STRUCTS_OTP_H 10 11 /** 12 * \file rp2350/otp.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/otp.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_otp 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/otp.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 typedef struct { 27 // (Description copied from array index 0 register OTP_SW_LOCK0 applies similarly to other array indexes) 28 _REG_(OTP_SW_LOCK0_OFFSET) // OTP_SW_LOCK0 29 // Software lock register for page 0. 30 // 0x0000000c [3:2] NSEC (-) Non-secure lock status 31 // 0x00000003 [1:0] SEC (-) Secure lock status 32 io_rw_32 sw_lock[64]; 33 34 _REG_(OTP_SBPI_INSTR_OFFSET) // OTP_SBPI_INSTR 35 // Dispatch instructions to the SBPI interface, used for programming the OTP fuses 36 // 0x40000000 [30] EXEC (0) Execute instruction 37 // 0x20000000 [29] IS_WR (0) Payload type is write 38 // 0x10000000 [28] HAS_PAYLOAD (0) Instruction has payload (data to be written or to be read) 39 // 0x0f000000 [27:24] PAYLOAD_SIZE_M1 (0x0) Instruction payload size in bytes minus 1 40 // 0x00ff0000 [23:16] TARGET (0x00) Instruction target, it can be PMC (0x3a) or DAP (0x02) 41 // 0x0000ff00 [15:8] CMD (0x00) 42 // 0x000000ff [7:0] SHORT_WDATA (0x00) wdata to be used only when payload_size_m1=0 43 io_rw_32 sbpi_instr; 44 45 // (Description copied from array index 0 register OTP_SBPI_WDATA_0 applies similarly to other array indexes) 46 _REG_(OTP_SBPI_WDATA_0_OFFSET) // OTP_SBPI_WDATA_0 47 // SBPI write payload bytes 3 48 // 0xffffffff [31:0] SBPI_WDATA_0 (0x00000000) 49 io_rw_32 sbpi_wdata[4]; 50 51 // (Description copied from array index 0 register OTP_SBPI_RDATA_0 applies similarly to other array indexes) 52 _REG_(OTP_SBPI_RDATA_0_OFFSET) // OTP_SBPI_RDATA_0 53 // Read payload bytes 3 54 // 0xffffffff [31:0] SBPI_RDATA_0 (0x00000000) 55 io_ro_32 sbpi_rdata[4]; 56 57 _REG_(OTP_SBPI_STATUS_OFFSET) // OTP_SBPI_STATUS 58 // 0x00ff0000 [23:16] MISO (-) SBPI MISO (master in - slave out): response from SBPI 59 // 0x00001000 [12] FLAG (-) SBPI flag 60 // 0x00000100 [8] INSTR_MISS (0) Last instruction missed (dropped), as the previous has... 61 // 0x00000010 [4] INSTR_DONE (0) Last instruction done 62 // 0x00000001 [0] RDATA_VLD (0) Read command has returned data 63 io_rw_32 sbpi_status; 64 65 _REG_(OTP_USR_OFFSET) // OTP_USR 66 // Controls for APB data read interface (USER interface) 67 // 0x00000010 [4] PD (0) Power-down; 1 disables current reference 68 // 0x00000001 [0] DCTRL (1) 1 enables USER interface; 0 disables USER interface... 69 io_rw_32 usr; 70 71 _REG_(OTP_DBG_OFFSET) // OTP_DBG 72 // Debug for OTP power-on state machine 73 // 0x00001000 [12] CUSTOMER_RMA_FLAG (-) The chip is in RMA mode 74 // 0x000000f0 [7:4] PSM_STATE (-) Monitor the PSM FSM's state 75 // 0x00000008 [3] ROSC_UP (-) Ring oscillator is up and running 76 // 0x00000004 [2] ROSC_UP_SEEN (0) Ring oscillator was seen up and running 77 // 0x00000002 [1] BOOT_DONE (-) PSM boot done status flag 78 // 0x00000001 [0] PSM_DONE (-) PSM done status flag 79 io_rw_32 dbg; 80 81 uint32_t _pad0; 82 83 _REG_(OTP_BIST_OFFSET) // OTP_BIST 84 // During BIST, count address locations that have at least one leaky bit 85 // 0x40000000 [30] CNT_FAIL (-) Flag if the count of address locations with at least one... 86 // 0x20000000 [29] CNT_CLR (0) Clear counter before use 87 // 0x10000000 [28] CNT_ENA (0) Enable the counter before the BIST function is initiated 88 // 0x0fff0000 [27:16] CNT_MAX (0xfff) The cnt_fail flag will be set if the number of leaky... 89 // 0x00001fff [12:0] CNT (-) Number of locations that have at least one leaky bit 90 io_rw_32 bist; 91 92 // (Description copied from array index 0 register OTP_CRT_KEY_W0 applies similarly to other array indexes) 93 _REG_(OTP_CRT_KEY_W0_OFFSET) // OTP_CRT_KEY_W0 94 // Word 0 (bits 31 95 // 0xffffffff [31:0] CRT_KEY_W0 (0x00000000) 96 io_wo_32 crt_key_w[4]; 97 98 _REG_(OTP_CRITICAL_OFFSET) // OTP_CRITICAL 99 // Quickly check values of critical flags read during boot up 100 // 0x00020000 [17] RISCV_DISABLE (0) 101 // 0x00010000 [16] ARM_DISABLE (0) 102 // 0x00000060 [6:5] GLITCH_DETECTOR_SENS (0x0) 103 // 0x00000010 [4] GLITCH_DETECTOR_ENABLE (0) 104 // 0x00000008 [3] DEFAULT_ARCHSEL (0) 105 // 0x00000004 [2] DEBUG_DISABLE (0) 106 // 0x00000002 [1] SECURE_DEBUG_DISABLE (0) 107 // 0x00000001 [0] SECURE_BOOT_ENABLE (0) 108 io_ro_32 critical; 109 110 _REG_(OTP_KEY_VALID_OFFSET) // OTP_KEY_VALID 111 // Which keys were valid (enrolled) at boot time 112 // 0x000000ff [7:0] KEY_VALID (0x00) 113 io_ro_32 key_valid; 114 115 _REG_(OTP_DEBUGEN_OFFSET) // OTP_DEBUGEN 116 // Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. 117 // 0x00000100 [8] MISC (0) Enable other debug components 118 // 0x00000008 [3] PROC1_SECURE (0) Permit core 1's Mem-AP to generate Secure accesses,... 119 // 0x00000004 [2] PROC1 (0) Enable core 1's Mem-AP if it is currently disabled 120 // 0x00000002 [1] PROC0_SECURE (0) Permit core 0's Mem-AP to generate Secure accesses,... 121 // 0x00000001 [0] PROC0 (0) Enable core 0's Mem-AP if it is currently disabled 122 io_rw_32 debugen; 123 124 _REG_(OTP_DEBUGEN_LOCK_OFFSET) // OTP_DEBUGEN_LOCK 125 // Write 1s to lock corresponding bits in DEBUGEN 126 // 0x00000100 [8] MISC (0) Write 1 to lock the MISC bit of DEBUGEN 127 // 0x00000008 [3] PROC1_SECURE (0) Write 1 to lock the PROC1_SECURE bit of DEBUGEN 128 // 0x00000004 [2] PROC1 (0) Write 1 to lock the PROC1 bit of DEBUGEN 129 // 0x00000002 [1] PROC0_SECURE (0) Write 1 to lock the PROC0_SECURE bit of DEBUGEN 130 // 0x00000001 [0] PROC0 (0) Write 1 to lock the PROC0 bit of DEBUGEN 131 io_rw_32 debugen_lock; 132 133 _REG_(OTP_ARCHSEL_OFFSET) // OTP_ARCHSEL 134 // Architecture select (Arm/RISC-V), applied on next processor reset. The default and allowable values of this register are constrained by the critical boot flags. 135 // 0x00000002 [1] CORE1 (0) Select architecture for core 1 136 // 0x00000001 [0] CORE0 (0) Select architecture for core 0 137 io_rw_32 archsel; 138 139 _REG_(OTP_ARCHSEL_STATUS_OFFSET) // OTP_ARCHSEL_STATUS 140 // Get the current architecture select state of each core 141 // 0x00000002 [1] CORE1 (0) Current architecture for core 0 142 // 0x00000001 [0] CORE0 (0) Current architecture for core 0 143 io_ro_32 archsel_status; 144 145 _REG_(OTP_BOOTDIS_OFFSET) // OTP_BOOTDIS 146 // Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. 147 // 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents 148 // 0x00000001 [0] NOW (0) When the core is powered down, the current value of... 149 io_rw_32 bootdis; 150 151 _REG_(OTP_INTR_OFFSET) // OTP_INTR 152 // Raw Interrupts 153 // 0x00000010 [4] APB_RD_NSEC_FAIL (0) 154 // 0x00000008 [3] APB_RD_SEC_FAIL (0) 155 // 0x00000004 [2] APB_DCTRL_FAIL (0) 156 // 0x00000002 [1] SBPI_WR_FAIL (0) 157 // 0x00000001 [0] SBPI_FLAG_N (0) 158 io_rw_32 intr; 159 160 _REG_(OTP_INTE_OFFSET) // OTP_INTE 161 // Interrupt Enable 162 // 0x00000010 [4] APB_RD_NSEC_FAIL (0) 163 // 0x00000008 [3] APB_RD_SEC_FAIL (0) 164 // 0x00000004 [2] APB_DCTRL_FAIL (0) 165 // 0x00000002 [1] SBPI_WR_FAIL (0) 166 // 0x00000001 [0] SBPI_FLAG_N (0) 167 io_rw_32 inte; 168 169 _REG_(OTP_INTF_OFFSET) // OTP_INTF 170 // Interrupt Force 171 // 0x00000010 [4] APB_RD_NSEC_FAIL (0) 172 // 0x00000008 [3] APB_RD_SEC_FAIL (0) 173 // 0x00000004 [2] APB_DCTRL_FAIL (0) 174 // 0x00000002 [1] SBPI_WR_FAIL (0) 175 // 0x00000001 [0] SBPI_FLAG_N (0) 176 io_rw_32 intf; 177 178 _REG_(OTP_INTS_OFFSET) // OTP_INTS 179 // Interrupt status after masking & forcing 180 // 0x00000010 [4] APB_RD_NSEC_FAIL (0) 181 // 0x00000008 [3] APB_RD_SEC_FAIL (0) 182 // 0x00000004 [2] APB_DCTRL_FAIL (0) 183 // 0x00000002 [1] SBPI_WR_FAIL (0) 184 // 0x00000001 [0] SBPI_FLAG_N (0) 185 io_ro_32 ints; 186 } otp_hw_t; 187 188 #define otp_hw ((otp_hw_t *)OTP_BASE) 189 static_assert(sizeof (otp_hw_t) == 0x0174, ""); 190 191 #endif // _HARDWARE_STRUCTS_OTP_H 192 193
