1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_DMA_H 9 #define _HARDWARE_STRUCTS_DMA_H 10 11 /** 12 * \file rp2040/dma.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/dma.h" 17 #include "hardware/structs/dma_debug.h" 18 19 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma 20 // 21 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 22 // _REG_(x) will link to the corresponding register in hardware/regs/dma.h. 23 // 24 // Bit-field descriptions are of the form: 25 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 26 27 typedef struct { 28 _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR 29 // DMA Channel 0 Read Address pointer 30 // 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes 31 io_rw_32 read_addr; 32 33 _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR 34 // DMA Channel 0 Write Address pointer 35 // 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes 36 io_rw_32 write_addr; 37 38 _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT 39 // DMA Channel 0 Transfer Count 40 // 0xffffffff [31:0] CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will... 41 io_rw_32 transfer_count; 42 43 _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG 44 // DMA Channel 0 Control and Status 45 // 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags 46 // 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error 47 // 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error 48 // 0x01000000 [24] BUSY (0) This flag goes high when the channel starts a new... 49 // 0x00800000 [23] SNIFF_EN (0) If 1, this channel's data transfers are visible to the... 50 // 0x00400000 [22] BSWAP (0) Apply byte-swap transformation to DMA data 51 // 0x00200000 [21] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the... 52 // 0x001f8000 [20:15] TREQ_SEL (0x00) Select a Transfer Request signal 53 // 0x00007800 [14:11] CHAIN_TO (0x0) When this channel completes, it will trigger the channel... 54 // 0x00000400 [10] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses 55 // 0x000003c0 [9:6] RING_SIZE (0x0) Size of address wrap region 56 // 0x00000020 [5] INCR_WRITE (0) If 1, the write address increments with each transfer 57 // 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer 58 // 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word) 59 // 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in... 60 // 0x00000001 [0] EN (0) DMA Channel Enable 61 io_rw_32 ctrl_trig; 62 63 _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL 64 // Alias for channel 0 CTRL register 65 // 0xffffffff [31:0] CH0_AL1_CTRL (-) 66 io_rw_32 al1_ctrl; 67 68 _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR 69 // Alias for channel 0 READ_ADDR register 70 // 0xffffffff [31:0] CH0_AL1_READ_ADDR (-) 71 io_rw_32 al1_read_addr; 72 73 _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR 74 // Alias for channel 0 WRITE_ADDR register 75 // 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-) 76 io_rw_32 al1_write_addr; 77 78 _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG 79 // Alias for channel 0 TRANS_COUNT register + 80 // 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-) 81 io_rw_32 al1_transfer_count_trig; 82 83 _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL 84 // Alias for channel 0 CTRL register 85 // 0xffffffff [31:0] CH0_AL2_CTRL (-) 86 io_rw_32 al2_ctrl; 87 88 _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT 89 // Alias for channel 0 TRANS_COUNT register 90 // 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-) 91 io_rw_32 al2_transfer_count; 92 93 _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR 94 // Alias for channel 0 READ_ADDR register 95 // 0xffffffff [31:0] CH0_AL2_READ_ADDR (-) 96 io_rw_32 al2_read_addr; 97 98 _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG 99 // Alias for channel 0 WRITE_ADDR register + 100 // 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-) 101 io_rw_32 al2_write_addr_trig; 102 103 _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL 104 // Alias for channel 0 CTRL register 105 // 0xffffffff [31:0] CH0_AL3_CTRL (-) 106 io_rw_32 al3_ctrl; 107 108 _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR 109 // Alias for channel 0 WRITE_ADDR register 110 // 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-) 111 io_rw_32 al3_write_addr; 112 113 _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT 114 // Alias for channel 0 TRANS_COUNT register 115 // 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-) 116 io_rw_32 al3_transfer_count; 117 118 _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG 119 // Alias for channel 0 READ_ADDR register + 120 // 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-) 121 io_rw_32 al3_read_addr_trig; 122 } dma_channel_hw_t; 123 124 typedef struct { 125 _REG_(DMA_INTR_OFFSET) // DMA_INTR 126 // Interrupt Status (raw) 127 // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 128 io_rw_32 intr; 129 130 _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 131 // Interrupt Enables for IRQ 0 132 // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 133 io_rw_32 inte; 134 135 _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 136 // Force Interrupts 137 // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 138 io_rw_32 intf; 139 140 _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 141 // Interrupt Status for IRQ 0 142 // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... 143 io_rw_32 ints; 144 } dma_irq_ctrl_hw_t; 145 146 typedef struct { 147 dma_channel_hw_t ch[12]; 148 149 uint32_t _pad0[64]; 150 151 union { 152 struct { 153 _REG_(DMA_INTR_OFFSET) // DMA_INTR 154 // Interrupt Status (raw) 155 // 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0 156 io_rw_32 intr; 157 158 _REG_(DMA_INTE0_OFFSET) // DMA_INTE0 159 // Interrupt Enables for IRQ 0 160 // 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0 161 io_rw_32 inte0; 162 163 _REG_(DMA_INTF0_OFFSET) // DMA_INTF0 164 // Force Interrupts 165 // 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0 166 io_rw_32 intf0; 167 168 _REG_(DMA_INTS0_OFFSET) // DMA_INTS0 169 // Interrupt Status for IRQ 0 170 // 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are... 171 io_rw_32 ints0; 172 173 uint32_t __pad0; 174 175 _REG_(DMA_INTE1_OFFSET) // DMA_INTE1 176 // Interrupt Enables for IRQ 1 177 // 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1 178 io_rw_32 inte1; 179 180 _REG_(DMA_INTF1_OFFSET) // DMA_INTF1 181 // Force Interrupts for IRQ 1 182 // 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1 183 io_rw_32 intf1; 184 185 _REG_(DMA_INTS1_OFFSET) // DMA_INTS1 186 // Interrupt Status (masked) for IRQ 1 187 // 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are... 188 io_rw_32 ints1; 189 }; 190 dma_irq_ctrl_hw_t irq_ctrl[2]; 191 }; 192 193 // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes) 194 _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0 195 // Pacing (X/Y) Fractional Timer + 196 // 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend 197 // 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor 198 io_rw_32 timer[4]; 199 200 _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER 201 // Trigger one or more channels simultaneously 202 // 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel 203 io_wo_32 multi_channel_trigger; 204 205 _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL 206 // Sniffer Control 207 // 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)... 208 // 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read 209 // 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,... 210 // 0x000001e0 [8:5] CALC (0x0) 211 // 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe 212 // 0x00000001 [0] EN (0) Enable sniffer 213 io_rw_32 sniff_ctrl; 214 215 _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA 216 // Data accumulator for sniff hardware 217 // 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA... 218 io_rw_32 sniff_data; 219 220 uint32_t _pad1; 221 222 _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS 223 // Debug RAF, WAF, TDF levels 224 // 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level 225 // 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level 226 // 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level 227 io_ro_32 fifo_levels; 228 229 _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT 230 // Abort an in-progress transfer sequence on one or more channels 231 // 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel 232 io_wo_32 abort; 233 } dma_hw_t; 234 235 #define dma_hw ((dma_hw_t *)DMA_BASE) 236 static_assert(sizeof (dma_hw_t) == 0x0448, ""); 237 238 #endif // _HARDWARE_STRUCTS_DMA_H 239 240
