1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_SIO_H 9 #define _HARDWARE_STRUCTS_SIO_H 10 11 /** 12 * \file rp2350/sio.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/sio.h" 17 #include "hardware/structs/interp.h" 18 19 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio 20 // 21 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 22 // _REG_(x) will link to the corresponding register in hardware/regs/sio.h. 23 // 24 // Bit-field descriptions are of the form: 25 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 26 27 28 typedef struct { 29 _REG_(SIO_CPUID_OFFSET) // SIO_CPUID 30 // Processor core identifier 31 // 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when... 32 io_ro_32 cpuid; 33 34 _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN 35 // Input value for GPIO0 36 // 0xffffffff [31:0] GPIO_IN (0x00000000) 37 io_ro_32 gpio_in; 38 39 _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN 40 // Input value on GPIO32 41 // 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins 42 // 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin 43 // 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin 44 // 0x02000000 [25] USB_DM (0) Input value on USB D- pin 45 // 0x01000000 [24] USB_DP (0) Input value on USB D+ pin 46 // 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32 47 io_ro_32 gpio_hi_in; 48 49 uint32_t _pad0; 50 51 _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT 52 // GPIO0 53 // 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0 54 io_rw_32 gpio_out; 55 56 _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT 57 // Output value for GPIO32 58 // 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins 59 // 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin 60 // 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin 61 // 0x02000000 [25] USB_DM (0) Output value for USB D- pin 62 // 0x01000000 [24] USB_DP (0) Output value for USB D+ pin 63 // 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32 64 io_rw_32 gpio_hi_out; 65 66 _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET 67 // GPIO0 68 // 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i 69 io_wo_32 gpio_set; 70 71 _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET 72 // Output value set for GPIO32 73 // 0xf0000000 [31:28] QSPI_SD (0x0) 74 // 0x08000000 [27] QSPI_CSN (0) 75 // 0x04000000 [26] QSPI_SCK (0) 76 // 0x02000000 [25] USB_DM (0) 77 // 0x01000000 [24] USB_DP (0) 78 // 0x0000ffff [15:0] GPIO (0x0000) 79 io_wo_32 gpio_hi_set; 80 81 _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR 82 // GPIO0 83 // 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i 84 io_wo_32 gpio_clr; 85 86 _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR 87 // Output value clear for GPIO32 88 // 0xf0000000 [31:28] QSPI_SD (0x0) 89 // 0x08000000 [27] QSPI_CSN (0) 90 // 0x04000000 [26] QSPI_SCK (0) 91 // 0x02000000 [25] USB_DM (0) 92 // 0x01000000 [24] USB_DP (0) 93 // 0x0000ffff [15:0] GPIO (0x0000) 94 io_wo_32 gpio_hi_clr; 95 96 _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR 97 // GPIO0 98 // 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i 99 io_wo_32 gpio_togl; 100 101 _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR 102 // Output value XOR for GPIO32 103 // 0xf0000000 [31:28] QSPI_SD (0x0) 104 // 0x08000000 [27] QSPI_CSN (0) 105 // 0x04000000 [26] QSPI_SCK (0) 106 // 0x02000000 [25] USB_DM (0) 107 // 0x01000000 [24] USB_DP (0) 108 // 0x0000ffff [15:0] GPIO (0x0000) 109 io_wo_32 gpio_hi_togl; 110 111 _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE 112 // GPIO0 113 // 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0 114 io_rw_32 gpio_oe; 115 116 _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE 117 // Output enable value for GPIO32 118 // 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2... 119 // 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin 120 // 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin 121 // 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin 122 // 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin 123 // 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32 124 io_rw_32 gpio_hi_oe; 125 126 _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET 127 // GPIO0 128 // 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i 129 io_wo_32 gpio_oe_set; 130 131 _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET 132 // Output enable set for GPIO32 133 // 0xf0000000 [31:28] QSPI_SD (0x0) 134 // 0x08000000 [27] QSPI_CSN (0) 135 // 0x04000000 [26] QSPI_SCK (0) 136 // 0x02000000 [25] USB_DM (0) 137 // 0x01000000 [24] USB_DP (0) 138 // 0x0000ffff [15:0] GPIO (0x0000) 139 io_wo_32 gpio_hi_oe_set; 140 141 _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR 142 // GPIO0 143 // 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i 144 io_wo_32 gpio_oe_clr; 145 146 _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR 147 // Output enable clear for GPIO32 148 // 0xf0000000 [31:28] QSPI_SD (0x0) 149 // 0x08000000 [27] QSPI_CSN (0) 150 // 0x04000000 [26] QSPI_SCK (0) 151 // 0x02000000 [25] USB_DM (0) 152 // 0x01000000 [24] USB_DP (0) 153 // 0x0000ffff [15:0] GPIO (0x0000) 154 io_wo_32 gpio_hi_oe_clr; 155 156 _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR 157 // GPIO0 158 // 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i 159 io_wo_32 gpio_oe_togl; 160 161 _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR 162 // Output enable XOR for GPIO32 163 // 0xf0000000 [31:28] QSPI_SD (0x0) 164 // 0x08000000 [27] QSPI_CSN (0) 165 // 0x04000000 [26] QSPI_SCK (0) 166 // 0x02000000 [25] USB_DM (0) 167 // 0x01000000 [24] USB_DP (0) 168 // 0x0000ffff [15:0] GPIO (0x0000) 169 io_wo_32 gpio_hi_oe_togl; 170 171 _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST 172 // Status register for inter-core FIFOs (mailboxes). 173 // 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty 174 // 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full 175 // 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i 176 // 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i 177 io_rw_32 fifo_st; 178 179 _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR 180 // Write access to this core's TX FIFO 181 // 0xffffffff [31:0] FIFO_WR (0x00000000) 182 io_wo_32 fifo_wr; 183 184 _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD 185 // Read access to this core's RX FIFO 186 // 0xffffffff [31:0] FIFO_RD (-) 187 io_ro_32 fifo_rd; 188 189 _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST 190 // Spinlock state 191 // 0xffffffff [31:0] SPINLOCK_ST (0x00000000) 192 io_ro_32 spinlock_st; 193 194 uint32_t _pad1[8]; 195 196 interp_hw_t interp[2]; 197 198 // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) 199 _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 200 // Spinlock register 0 201 // 0xffffffff [31:0] SPINLOCK0 (0x00000000) 202 io_rw_32 spinlock[32]; 203 204 _REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET 205 // Trigger a doorbell interrupt on the opposite core 206 // 0x000000ff [7:0] DOORBELL_OUT_SET (0x00) 207 io_rw_32 doorbell_out_set; 208 209 _REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR 210 // Clear doorbells which have been posted to the opposite core 211 // 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00) 212 io_rw_32 doorbell_out_clr; 213 214 _REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET 215 // Write 1s to trigger doorbell interrupts on this core 216 // 0x000000ff [7:0] DOORBELL_IN_SET (0x00) 217 io_rw_32 doorbell_in_set; 218 219 _REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR 220 // Check and acknowledge doorbells posted to this core 221 // 0x000000ff [7:0] DOORBELL_IN_CLR (0x00) 222 io_rw_32 doorbell_in_clr; 223 224 _REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC 225 // Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so... 226 // 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure... 227 // 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the... 228 // 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the... 229 io_rw_32 peri_nonsec; 230 231 uint32_t _pad2[3]; 232 233 _REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ 234 // Control the assertion of the standard software interrupt (MIP 235 // 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag 236 // 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag 237 // 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag 238 // 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag 239 io_rw_32 riscv_softirq; 240 241 _REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL 242 // Control register for the RISC-V 64-bit Machine-mode timer 243 // 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state 244 // 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state 245 // 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i 246 // 0x00000001 [0] EN (1) Timer enable bit 247 io_rw_32 mtime_ctrl; 248 249 uint32_t _pad3[2]; 250 251 _REG_(SIO_MTIME_OFFSET) // SIO_MTIME 252 // Read/write access to the high half of RISC-V Machine-mode timer 253 // 0xffffffff [31:0] MTIME (0x00000000) 254 io_rw_32 mtime; 255 256 _REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH 257 // Read/write access to the high half of RISC-V Machine-mode timer 258 // 0xffffffff [31:0] MTIMEH (0x00000000) 259 io_rw_32 mtimeh; 260 261 _REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP 262 // Low half of RISC-V Machine-mode timer comparator 263 // 0xffffffff [31:0] MTIMECMP (0xffffffff) 264 io_rw_32 mtimecmp; 265 266 _REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH 267 // High half of RISC-V Machine-mode timer comparator 268 // 0xffffffff [31:0] MTIMECMPH (0xffffffff) 269 io_rw_32 mtimecmph; 270 271 _REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL 272 // Control register for TMDS encoder 273 // 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders 274 // 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle... 275 // 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read... 276 // 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE 277 // 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,... 278 // 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,... 279 // 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,... 280 // 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... 281 // 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... 282 // 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by... 283 io_rw_32 tmds_ctrl; 284 285 _REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA 286 // Write-only access to the TMDS colour data register 287 // 0xffffffff [31:0] TMDS_WDATA (0x00000000) 288 io_wo_32 tmds_wdata; 289 290 _REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE 291 // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols) 292 // 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000) 293 io_ro_32 tmds_peek_single; 294 295 _REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE 296 // Get the encoding of one pixel's worth of colour data, packed into a 32-bit value 297 // 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000) 298 io_ro_32 tmds_pop_single; 299 300 _REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0 301 // Get lane 0 of the encoding of two pixels' worth of colour data 302 // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000) 303 io_ro_32 tmds_peek_double_l0; 304 305 _REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0 306 // Get lane 0 of the encoding of two pixels' worth of colour data 307 // 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000) 308 io_ro_32 tmds_pop_double_l0; 309 310 _REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1 311 // Get lane 1 of the encoding of two pixels' worth of colour data 312 // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000) 313 io_ro_32 tmds_peek_double_l1; 314 315 _REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1 316 // Get lane 1 of the encoding of two pixels' worth of colour data 317 // 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000) 318 io_ro_32 tmds_pop_double_l1; 319 320 _REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2 321 // Get lane 2 of the encoding of two pixels' worth of colour data 322 // 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000) 323 io_ro_32 tmds_peek_double_l2; 324 325 _REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2 326 // Get lane 2 of the encoding of two pixels' worth of colour data 327 // 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000) 328 io_ro_32 tmds_pop_double_l2; 329 } sio_hw_t; 330 331 #define sio_hw ((sio_hw_t *)SIO_BASE) 332 #define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE) 333 static_assert(sizeof (sio_hw_t) == 0x01e8, ""); 334 335 #endif // _HARDWARE_STRUCTS_SIO_H 336 337
