Searched refs:__O (Results 1 – 25 of 86) sorted by relevance
1234
146 …__O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Regist…150 …__O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Re…151 …__O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Re…154 …__O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Contro…
238 __O ICM_CTRL_Type CTRL; /**< \brief Offset: 0x04 ( /W 32) Control */241 __O ICM_IER_Type IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */242 __O ICM_IDR_Type IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */249 …__O ICM_UIHVAL_Type UIHVAL[8]; /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Va…
117 …__O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Reg…118 …__O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Re…
166 __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */169 …__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vecto…
230 __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */231 __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */
221 __O QSPI_TXDATA_Type TXDATA; /**< \brief Offset: 0x10 ( /W 32) Transmit Data */232 __O QSPI_SCRAMBKEY_Type SCRAMBKEY; /**< \brief Offset: 0x44 ( /W 32) Scrambling Key */
116 __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
806 …__O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT E…807 …__O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT E…822 …__O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point…823 …__O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point…
116 …__O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
752 …__O SDHC_FERACES_Type FERACES; /**< \brief Offset: 0x050 ( /W 16) Force Event for Aut…753 …__O SDHC_FEREIS_Type FEREIS; /**< \brief Offset: 0x052 ( /W 16) Force Event for Err…765 __O SDHC_MC2R_Type MC2R; /**< \brief Offset: 0x205 ( /W 8) MMC Control 2 */
190 …__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration …
200 …__O uint32_t CMCC_CTRL; /**< Offset: 0x08 ( /W 32) Cache Control…204 …__O uint32_t CMCC_MAINT0; /**< Offset: 0x20 ( /W 32) Cache Mainten…205 …__O uint32_t CMCC_MAINT1; /**< Offset: 0x24 ( /W 32) Cache Mainten…208 …__O uint32_t CMCC_MCTRL; /**< Offset: 0x30 ( /W 32) Cache Monitor…
170 …__O uint32_t PCC_IER; /**< Offset: 0x04 ( /W 32) Interrupt Ena…171 …__O uint32_t PCC_IDR; /**< Offset: 0x08 ( /W 32) Interrupt Dis…
389 __O uint32_t ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control */392 …__O uint32_t ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Ena…393 …__O uint32_t ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Dis…400 …__O uint32_t ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial …
300 __O uint32_t AES_KEYWORD[8]; /**< Offset: 0x0C ( /W 32) Keyword n */303 …__O uint32_t AES_INTVECTV[4]; /**< Offset: 0x3C ( /W 32) Initialisatio…
200 …__O uint32_t CMCC_CTRL; /* Offset: 0x08 ( /W 32) Cache Control R…204 …__O uint32_t CMCC_MAINT0; /* Offset: 0x20 ( /W 32) Cache Maintenan…205 …__O uint32_t CMCC_MAINT1; /* Offset: 0x24 ( /W 32) Cache Maintenan…208 …__O uint32_t CMCC_MCTRL; /* Offset: 0x30 ( /W 32) Cache Monitor C…
170 …__O uint32_t PCC_IER; /* Offset: 0x04 ( /W 32) Interrupt Enabl…171 …__O uint32_t PCC_IDR; /* Offset: 0x08 ( /W 32) Interrupt Disab…
389 __O uint32_t ICM_CTRL; /* Offset: 0x04 ( /W 32) Control */392 …__O uint32_t ICM_IER; /* Offset: 0x10 ( /W 32) Interrupt Enabl…393 …__O uint32_t ICM_IDR; /* Offset: 0x14 ( /W 32) Interrupt Disab…400 …__O uint32_t ICM_UIHVAL[8]; /* Offset: 0x38 ( /W 32) User Initial Ha…
300 __O uint32_t AES_KEYWORD[8]; /* Offset: 0x0C ( /W 32) Keyword n */303 …__O uint32_t AES_INTVECTV[4]; /* Offset: 0x3C ( /W 32) Initialisation …
34 #ifndef __O35 #define __O volatile macro
35 #ifndef __O36 #define __O volatile macro232 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_NV_MAP_DDR_PHY_TypeDef NV_MAP_DDR_PHY :1;233 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_V_MAP_DDR_PHY_TypeDef V_MAP_DDR_PHY :1;235 __O CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_PERIPH_DDR_PHY_TypeDef PERIPH_DDR_PHY :1;295 __O CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_NV_MAP_MAIN_PLL_TypeDef NV_MAP_MAIN_PLL :1;296 __O CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_V_MAP_MAIN_PLL_TypeDef V_MAP_MAIN_PLL :1;298 __O CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_PERIPH_MAIN_PLL_TypeDef PERIPH_MAIN_PLL :1;498 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_NV_MAP_IOSCB_PLL_TypeDef NV_MAP_IOSCB_PLL :1;499 __O CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_V_MAP_IOSCB_PLL_TypeDef V_MAP_IOSCB_PLL :1;[all …]
85 #ifndef __O86 #define __O volatile macro
