1 /* 2 * Component description for CMCC 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_CMCC_COMPONENT_H_ 22 #define _PIC32CXSG41_CMCC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR CMCC */ 26 /* ************************************************************************** */ 27 28 /* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */ 29 #define CMCC_TYPE_RESETVALUE _UINT32_(0x12D2) /* (CMCC_TYPE) Cache Type Register Reset Value */ 30 31 #define CMCC_TYPE_GCLK_Pos _UINT32_(1) /* (CMCC_TYPE) dynamic Clock Gating supported Position */ 32 #define CMCC_TYPE_GCLK_Msk (_UINT32_(0x1) << CMCC_TYPE_GCLK_Pos) /* (CMCC_TYPE) dynamic Clock Gating supported Mask */ 33 #define CMCC_TYPE_GCLK(value) (CMCC_TYPE_GCLK_Msk & (_UINT32_(value) << CMCC_TYPE_GCLK_Pos)) /* Assignment of value for GCLK in the CMCC_TYPE register */ 34 #define CMCC_TYPE_RRP_Pos _UINT32_(4) /* (CMCC_TYPE) Round Robin Policy supported Position */ 35 #define CMCC_TYPE_RRP_Msk (_UINT32_(0x1) << CMCC_TYPE_RRP_Pos) /* (CMCC_TYPE) Round Robin Policy supported Mask */ 36 #define CMCC_TYPE_RRP(value) (CMCC_TYPE_RRP_Msk & (_UINT32_(value) << CMCC_TYPE_RRP_Pos)) /* Assignment of value for RRP in the CMCC_TYPE register */ 37 #define CMCC_TYPE_WAYNUM_Pos _UINT32_(5) /* (CMCC_TYPE) Number of Way Position */ 38 #define CMCC_TYPE_WAYNUM_Msk (_UINT32_(0x3) << CMCC_TYPE_WAYNUM_Pos) /* (CMCC_TYPE) Number of Way Mask */ 39 #define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & (_UINT32_(value) << CMCC_TYPE_WAYNUM_Pos)) /* Assignment of value for WAYNUM in the CMCC_TYPE register */ 40 #define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _UINT32_(0x2) /* (CMCC_TYPE) 4-WAY set associative */ 41 #define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) /* (CMCC_TYPE) 4-WAY set associative Position */ 42 #define CMCC_TYPE_LCKDOWN_Pos _UINT32_(7) /* (CMCC_TYPE) Lock Down supported Position */ 43 #define CMCC_TYPE_LCKDOWN_Msk (_UINT32_(0x1) << CMCC_TYPE_LCKDOWN_Pos) /* (CMCC_TYPE) Lock Down supported Mask */ 44 #define CMCC_TYPE_LCKDOWN(value) (CMCC_TYPE_LCKDOWN_Msk & (_UINT32_(value) << CMCC_TYPE_LCKDOWN_Pos)) /* Assignment of value for LCKDOWN in the CMCC_TYPE register */ 45 #define CMCC_TYPE_CSIZE_Pos _UINT32_(8) /* (CMCC_TYPE) Cache Size Position */ 46 #define CMCC_TYPE_CSIZE_Msk (_UINT32_(0x7) << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size Mask */ 47 #define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & (_UINT32_(value) << CMCC_TYPE_CSIZE_Pos)) /* Assignment of value for CSIZE in the CMCC_TYPE register */ 48 #define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _UINT32_(0x0) /* (CMCC_TYPE) Cache Size is 1 KB */ 49 #define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _UINT32_(0x1) /* (CMCC_TYPE) Cache Size is 2 KB */ 50 #define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _UINT32_(0x2) /* (CMCC_TYPE) Cache Size is 4 KB */ 51 #define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 1 KB Position */ 52 #define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 2 KB Position */ 53 #define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) /* (CMCC_TYPE) Cache Size is 4 KB Position */ 54 #define CMCC_TYPE_CLSIZE_Pos _UINT32_(11) /* (CMCC_TYPE) Cache Line Size Position */ 55 #define CMCC_TYPE_CLSIZE_Msk (_UINT32_(0x7) << CMCC_TYPE_CLSIZE_Pos) /* (CMCC_TYPE) Cache Line Size Mask */ 56 #define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & (_UINT32_(value) << CMCC_TYPE_CLSIZE_Pos)) /* Assignment of value for CLSIZE in the CMCC_TYPE register */ 57 #define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _UINT32_(0x2) /* (CMCC_TYPE) Cache Line Size is 16 bytes */ 58 #define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) /* (CMCC_TYPE) Cache Line Size is 16 bytes Position */ 59 #define CMCC_TYPE_Msk _UINT32_(0x00003FF2) /* (CMCC_TYPE) Register Mask */ 60 61 62 /* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ 63 #define CMCC_CFG_RESETVALUE _UINT32_(0x20) /* (CMCC_CFG) Cache Configuration Register Reset Value */ 64 65 #define CMCC_CFG_ICDIS_Pos _UINT32_(1) /* (CMCC_CFG) Instruction Cache Disable Position */ 66 #define CMCC_CFG_ICDIS_Msk (_UINT32_(0x1) << CMCC_CFG_ICDIS_Pos) /* (CMCC_CFG) Instruction Cache Disable Mask */ 67 #define CMCC_CFG_ICDIS(value) (CMCC_CFG_ICDIS_Msk & (_UINT32_(value) << CMCC_CFG_ICDIS_Pos)) /* Assignment of value for ICDIS in the CMCC_CFG register */ 68 #define CMCC_CFG_DCDIS_Pos _UINT32_(2) /* (CMCC_CFG) Data Cache Disable Position */ 69 #define CMCC_CFG_DCDIS_Msk (_UINT32_(0x1) << CMCC_CFG_DCDIS_Pos) /* (CMCC_CFG) Data Cache Disable Mask */ 70 #define CMCC_CFG_DCDIS(value) (CMCC_CFG_DCDIS_Msk & (_UINT32_(value) << CMCC_CFG_DCDIS_Pos)) /* Assignment of value for DCDIS in the CMCC_CFG register */ 71 #define CMCC_CFG_CSIZESW_Pos _UINT32_(4) /* (CMCC_CFG) Cache size configured by software Position */ 72 #define CMCC_CFG_CSIZESW_Msk (_UINT32_(0x7) << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) Cache size configured by software Mask */ 73 #define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & (_UINT32_(value) << CMCC_CFG_CSIZESW_Pos)) /* Assignment of value for CSIZESW in the CMCC_CFG register */ 74 #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _UINT32_(0x0) /* (CMCC_CFG) The Cache Size is configured to 1KB */ 75 #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _UINT32_(0x1) /* (CMCC_CFG) The Cache Size is configured to 2KB */ 76 #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _UINT32_(0x2) /* (CMCC_CFG) The Cache Size is configured to 4KB */ 77 #define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 1KB Position */ 78 #define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 2KB Position */ 79 #define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) /* (CMCC_CFG) The Cache Size is configured to 4KB Position */ 80 #define CMCC_CFG_Msk _UINT32_(0x00000076) /* (CMCC_CFG) Register Mask */ 81 82 83 /* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ 84 #define CMCC_CTRL_RESETVALUE _UINT32_(0x00) /* (CMCC_CTRL) Cache Control Register Reset Value */ 85 86 #define CMCC_CTRL_CEN_Pos _UINT32_(0) /* (CMCC_CTRL) Cache Controller Enable Position */ 87 #define CMCC_CTRL_CEN_Msk (_UINT32_(0x1) << CMCC_CTRL_CEN_Pos) /* (CMCC_CTRL) Cache Controller Enable Mask */ 88 #define CMCC_CTRL_CEN(value) (CMCC_CTRL_CEN_Msk & (_UINT32_(value) << CMCC_CTRL_CEN_Pos)) /* Assignment of value for CEN in the CMCC_CTRL register */ 89 #define CMCC_CTRL_Msk _UINT32_(0x00000001) /* (CMCC_CTRL) Register Mask */ 90 91 92 /* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */ 93 #define CMCC_SR_RESETVALUE _UINT32_(0x00) /* (CMCC_SR) Cache Status Register Reset Value */ 94 95 #define CMCC_SR_CSTS_Pos _UINT32_(0) /* (CMCC_SR) Cache Controller Status Position */ 96 #define CMCC_SR_CSTS_Msk (_UINT32_(0x1) << CMCC_SR_CSTS_Pos) /* (CMCC_SR) Cache Controller Status Mask */ 97 #define CMCC_SR_CSTS(value) (CMCC_SR_CSTS_Msk & (_UINT32_(value) << CMCC_SR_CSTS_Pos)) /* Assignment of value for CSTS in the CMCC_SR register */ 98 #define CMCC_SR_Msk _UINT32_(0x00000001) /* (CMCC_SR) Register Mask */ 99 100 101 /* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ 102 #define CMCC_LCKWAY_RESETVALUE _UINT32_(0x00) /* (CMCC_LCKWAY) Cache Lock per Way Register Reset Value */ 103 104 #define CMCC_LCKWAY_LCKWAY_Pos _UINT32_(0) /* (CMCC_LCKWAY) Lockdown way Register Position */ 105 #define CMCC_LCKWAY_LCKWAY_Msk (_UINT32_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) /* (CMCC_LCKWAY) Lockdown way Register Mask */ 106 #define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & (_UINT32_(value) << CMCC_LCKWAY_LCKWAY_Pos)) /* Assignment of value for LCKWAY in the CMCC_LCKWAY register */ 107 #define CMCC_LCKWAY_Msk _UINT32_(0x0000000F) /* (CMCC_LCKWAY) Register Mask */ 108 109 110 /* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ 111 #define CMCC_MAINT0_RESETVALUE _UINT32_(0x00) /* (CMCC_MAINT0) Cache Maintenance Register 0 Reset Value */ 112 113 #define CMCC_MAINT0_INVALL_Pos _UINT32_(0) /* (CMCC_MAINT0) Cache Controller invalidate All Position */ 114 #define CMCC_MAINT0_INVALL_Msk (_UINT32_(0x1) << CMCC_MAINT0_INVALL_Pos) /* (CMCC_MAINT0) Cache Controller invalidate All Mask */ 115 #define CMCC_MAINT0_INVALL(value) (CMCC_MAINT0_INVALL_Msk & (_UINT32_(value) << CMCC_MAINT0_INVALL_Pos)) /* Assignment of value for INVALL in the CMCC_MAINT0 register */ 116 #define CMCC_MAINT0_Msk _UINT32_(0x00000001) /* (CMCC_MAINT0) Register Mask */ 117 118 119 /* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ 120 #define CMCC_MAINT1_RESETVALUE _UINT32_(0x00) /* (CMCC_MAINT1) Cache Maintenance Register 1 Reset Value */ 121 122 #define CMCC_MAINT1_INDEX_Pos _UINT32_(4) /* (CMCC_MAINT1) Invalidate Index Position */ 123 #define CMCC_MAINT1_INDEX_Msk (_UINT32_(0xFF) << CMCC_MAINT1_INDEX_Pos) /* (CMCC_MAINT1) Invalidate Index Mask */ 124 #define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & (_UINT32_(value) << CMCC_MAINT1_INDEX_Pos)) /* Assignment of value for INDEX in the CMCC_MAINT1 register */ 125 #define CMCC_MAINT1_WAY_Pos _UINT32_(28) /* (CMCC_MAINT1) Invalidate Way Position */ 126 #define CMCC_MAINT1_WAY_Msk (_UINT32_(0xF) << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Invalidate Way Mask */ 127 #define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & (_UINT32_(value) << CMCC_MAINT1_WAY_Pos)) /* Assignment of value for WAY in the CMCC_MAINT1 register */ 128 #define CMCC_MAINT1_WAY_WAY0_Val _UINT32_(0x0) /* (CMCC_MAINT1) Way 0 is selection for index invalidation */ 129 #define CMCC_MAINT1_WAY_WAY1_Val _UINT32_(0x1) /* (CMCC_MAINT1) Way 1 is selection for index invalidation */ 130 #define CMCC_MAINT1_WAY_WAY2_Val _UINT32_(0x2) /* (CMCC_MAINT1) Way 2 is selection for index invalidation */ 131 #define CMCC_MAINT1_WAY_WAY3_Val _UINT32_(0x3) /* (CMCC_MAINT1) Way 3 is selection for index invalidation */ 132 #define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 0 is selection for index invalidation Position */ 133 #define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 1 is selection for index invalidation Position */ 134 #define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 2 is selection for index invalidation Position */ 135 #define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) /* (CMCC_MAINT1) Way 3 is selection for index invalidation Position */ 136 #define CMCC_MAINT1_Msk _UINT32_(0xF0000FF0) /* (CMCC_MAINT1) Register Mask */ 137 138 139 /* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ 140 #define CMCC_MCFG_RESETVALUE _UINT32_(0x00) /* (CMCC_MCFG) Cache Monitor Configuration Register Reset Value */ 141 142 #define CMCC_MCFG_MODE_Pos _UINT32_(0) /* (CMCC_MCFG) Cache Controller Monitor Counter Mode Position */ 143 #define CMCC_MCFG_MODE_Msk (_UINT32_(0x3) << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Cache Controller Monitor Counter Mode Mask */ 144 #define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & (_UINT32_(value) << CMCC_MCFG_MODE_Pos)) /* Assignment of value for MODE in the CMCC_MCFG register */ 145 #define CMCC_MCFG_MODE_CYCLE_COUNT_Val _UINT32_(0x0) /* (CMCC_MCFG) Cycle counter */ 146 #define CMCC_MCFG_MODE_IHIT_COUNT_Val _UINT32_(0x1) /* (CMCC_MCFG) Instruction hit counter */ 147 #define CMCC_MCFG_MODE_DHIT_COUNT_Val _UINT32_(0x2) /* (CMCC_MCFG) Data hit counter */ 148 #define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Cycle counter Position */ 149 #define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Instruction hit counter Position */ 150 #define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) /* (CMCC_MCFG) Data hit counter Position */ 151 #define CMCC_MCFG_Msk _UINT32_(0x00000003) /* (CMCC_MCFG) Register Mask */ 152 153 154 /* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ 155 #define CMCC_MEN_RESETVALUE _UINT32_(0x00) /* (CMCC_MEN) Cache Monitor Enable Register Reset Value */ 156 157 #define CMCC_MEN_MENABLE_Pos _UINT32_(0) /* (CMCC_MEN) Cache Controller Monitor Enable Position */ 158 #define CMCC_MEN_MENABLE_Msk (_UINT32_(0x1) << CMCC_MEN_MENABLE_Pos) /* (CMCC_MEN) Cache Controller Monitor Enable Mask */ 159 #define CMCC_MEN_MENABLE(value) (CMCC_MEN_MENABLE_Msk & (_UINT32_(value) << CMCC_MEN_MENABLE_Pos)) /* Assignment of value for MENABLE in the CMCC_MEN register */ 160 #define CMCC_MEN_Msk _UINT32_(0x00000001) /* (CMCC_MEN) Register Mask */ 161 162 163 /* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ 164 #define CMCC_MCTRL_RESETVALUE _UINT32_(0x00) /* (CMCC_MCTRL) Cache Monitor Control Register Reset Value */ 165 166 #define CMCC_MCTRL_SWRST_Pos _UINT32_(0) /* (CMCC_MCTRL) Cache Controller Software Reset Position */ 167 #define CMCC_MCTRL_SWRST_Msk (_UINT32_(0x1) << CMCC_MCTRL_SWRST_Pos) /* (CMCC_MCTRL) Cache Controller Software Reset Mask */ 168 #define CMCC_MCTRL_SWRST(value) (CMCC_MCTRL_SWRST_Msk & (_UINT32_(value) << CMCC_MCTRL_SWRST_Pos)) /* Assignment of value for SWRST in the CMCC_MCTRL register */ 169 #define CMCC_MCTRL_Msk _UINT32_(0x00000001) /* (CMCC_MCTRL) Register Mask */ 170 171 172 /* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */ 173 #define CMCC_MSR_RESETVALUE _UINT32_(0x00) /* (CMCC_MSR) Cache Monitor Status Register Reset Value */ 174 175 #define CMCC_MSR_EVENT_CNT_Pos _UINT32_(0) /* (CMCC_MSR) Monitor Event Counter Position */ 176 #define CMCC_MSR_EVENT_CNT_Msk (_UINT32_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) /* (CMCC_MSR) Monitor Event Counter Mask */ 177 #define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & (_UINT32_(value) << CMCC_MSR_EVENT_CNT_Pos)) /* Assignment of value for EVENT_CNT in the CMCC_MSR register */ 178 #define CMCC_MSR_Msk _UINT32_(0xFFFFFFFF) /* (CMCC_MSR) Register Mask */ 179 180 181 /* CMCC register offsets definitions */ 182 #define CMCC_TYPE_REG_OFST _UINT32_(0x00) /* (CMCC_TYPE) Cache Type Register Offset */ 183 #define CMCC_CFG_REG_OFST _UINT32_(0x04) /* (CMCC_CFG) Cache Configuration Register Offset */ 184 #define CMCC_CTRL_REG_OFST _UINT32_(0x08) /* (CMCC_CTRL) Cache Control Register Offset */ 185 #define CMCC_SR_REG_OFST _UINT32_(0x0C) /* (CMCC_SR) Cache Status Register Offset */ 186 #define CMCC_LCKWAY_REG_OFST _UINT32_(0x10) /* (CMCC_LCKWAY) Cache Lock per Way Register Offset */ 187 #define CMCC_MAINT0_REG_OFST _UINT32_(0x20) /* (CMCC_MAINT0) Cache Maintenance Register 0 Offset */ 188 #define CMCC_MAINT1_REG_OFST _UINT32_(0x24) /* (CMCC_MAINT1) Cache Maintenance Register 1 Offset */ 189 #define CMCC_MCFG_REG_OFST _UINT32_(0x28) /* (CMCC_MCFG) Cache Monitor Configuration Register Offset */ 190 #define CMCC_MEN_REG_OFST _UINT32_(0x2C) /* (CMCC_MEN) Cache Monitor Enable Register Offset */ 191 #define CMCC_MCTRL_REG_OFST _UINT32_(0x30) /* (CMCC_MCTRL) Cache Monitor Control Register Offset */ 192 #define CMCC_MSR_REG_OFST _UINT32_(0x34) /* (CMCC_MSR) Cache Monitor Status Register Offset */ 193 194 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 195 /* CMCC register API structure */ 196 typedef struct 197 { /* Cortex M Cache Controller */ 198 __I uint32_t CMCC_TYPE; /* Offset: 0x00 (R/ 32) Cache Type Register */ 199 __IO uint32_t CMCC_CFG; /* Offset: 0x04 (R/W 32) Cache Configuration Register */ 200 __O uint32_t CMCC_CTRL; /* Offset: 0x08 ( /W 32) Cache Control Register */ 201 __I uint32_t CMCC_SR; /* Offset: 0x0C (R/ 32) Cache Status Register */ 202 __IO uint32_t CMCC_LCKWAY; /* Offset: 0x10 (R/W 32) Cache Lock per Way Register */ 203 __I uint8_t Reserved1[0x0C]; 204 __O uint32_t CMCC_MAINT0; /* Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ 205 __O uint32_t CMCC_MAINT1; /* Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ 206 __IO uint32_t CMCC_MCFG; /* Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ 207 __IO uint32_t CMCC_MEN; /* Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ 208 __O uint32_t CMCC_MCTRL; /* Offset: 0x30 ( /W 32) Cache Monitor Control Register */ 209 __I uint32_t CMCC_MSR; /* Offset: 0x34 (R/ 32) Cache Monitor Status Register */ 210 } cmcc_registers_t; 211 212 213 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 214 #endif /* _PIC32CXSG41_CMCC_COMPONENT_H_ */ 215
