1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_ICM_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_ICM_COMPONENT_FIXUP_H_ 9 10 /* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 uint32_t reg; /*!< Type used for register access */ 14 } ICM_RADDR_Type; 15 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 16 17 /* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */ 18 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 19 typedef union { 20 struct { 21 uint32_t CDWBN:1; /*!< bit: 0 Compare Digest Write Back */ 22 uint32_t WRAP:1; /*!< bit: 1 Region Wrap */ 23 uint32_t EOM:1; /*!< bit: 2 End of Monitoring */ 24 uint32_t :1; /*!< bit: 3 Reserved */ 25 uint32_t RHIEN:1; /*!< bit: 4 Region Hash Interrupt Enable */ 26 uint32_t DMIEN:1; /*!< bit: 5 Region Digest Mismatch Interrupt Enable */ 27 uint32_t BEIEN:1; /*!< bit: 6 Region Bus Error Interrupt Enable */ 28 uint32_t WCIEN:1; /*!< bit: 7 Region Wrap Condition Detected Interrupt Enable */ 29 uint32_t ECIEN:1; /*!< bit: 8 Region End bit Condition detected Interrupt Enable */ 30 uint32_t SUIEN:1; /*!< bit: 9 Region Status Updated Interrupt Enable */ 31 uint32_t PROCDLY:1; /*!< bit: 10 SHA Processing Delay */ 32 uint32_t :1; /*!< bit: 11 Reserved */ 33 uint32_t ALGO:3; /*!< bit: 12..14 SHA Algorithm */ 34 uint32_t :9; /*!< bit: 15..23 Reserved */ 35 uint32_t MRPROT:6; /*!< bit: 24..29 Memory Region AHB Protection */ 36 uint32_t :2; /*!< bit: 30..31 Reserved */ 37 } bit; /*!< Structure used for bit access */ 38 uint32_t reg; /*!< Type used for register access */ 39 } ICM_RCFG_Type; 40 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 41 42 /* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t TRSIZE:16; /*!< bit: 0..15 Transfer Size */ 47 uint32_t :16; /*!< bit: 16..31 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } ICM_RCTRL_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 /* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */ 54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 55 typedef union { 56 uint32_t reg; /*!< Type used for register access */ 57 } ICM_RNEXT_Type; 58 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 /* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */ 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 typedef union { 63 struct { 64 uint32_t WBDIS:1; /*!< bit: 0 Write Back Disable */ 65 uint32_t EOMDIS:1; /*!< bit: 1 End of Monitoring Disable */ 66 uint32_t SLBDIS:1; /*!< bit: 2 Secondary List Branching Disable */ 67 uint32_t :1; /*!< bit: 3 Reserved */ 68 uint32_t BBC:4; /*!< bit: 4.. 7 Bus Burden Control */ 69 uint32_t ASCD:1; /*!< bit: 8 Automatic Switch To Compare Digest */ 70 uint32_t DUALBUFF:1; /*!< bit: 9 Dual Input Buffer */ 71 uint32_t :2; /*!< bit: 10..11 Reserved */ 72 uint32_t UIHASH:1; /*!< bit: 12 User Initial Hash Value */ 73 uint32_t UALGO:3; /*!< bit: 13..15 User SHA Algorithm */ 74 uint32_t HAPROT:6; /*!< bit: 16..21 Region Hash Area Protection */ 75 uint32_t :2; /*!< bit: 22..23 Reserved */ 76 uint32_t DAPROT:6; /*!< bit: 24..29 Region Descriptor Area Protection */ 77 uint32_t :2; /*!< bit: 30..31 Reserved */ 78 } bit; /*!< Structure used for bit access */ 79 uint32_t reg; /*!< Type used for register access */ 80 } ICM_CFG_Type; 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 /* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */ 83 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 84 typedef union { 85 struct { 86 uint32_t ENABLE:1; /*!< bit: 0 ICM Enable */ 87 uint32_t DISABLE:1; /*!< bit: 1 ICM Disable Register */ 88 uint32_t SWRST:1; /*!< bit: 2 Software Reset */ 89 uint32_t :1; /*!< bit: 3 Reserved */ 90 uint32_t REHASH:4; /*!< bit: 4.. 7 Recompute Internal Hash */ 91 uint32_t RMDIS:4; /*!< bit: 8..11 Region Monitoring Disable */ 92 uint32_t RMEN:4; /*!< bit: 12..15 Region Monitoring Enable */ 93 uint32_t :16; /*!< bit: 16..31 Reserved */ 94 } bit; /*!< Structure used for bit access */ 95 uint32_t reg; /*!< Type used for register access */ 96 } ICM_CTRL_Type; 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 /* -------- ICM_SR : (ICM Offset: 0x08) ( R/ 32) Status -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint32_t ENABLE:1; /*!< bit: 0 ICM Controller Enable Register */ 104 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 105 uint32_t RAWRMDIS:4; /*!< bit: 8..11 RAW Region Monitoring Disabled Status */ 106 uint32_t RMDIS:4; /*!< bit: 12..15 Region Monitoring Disabled Status */ 107 uint32_t :16; /*!< bit: 16..31 Reserved */ 108 } bit; /*!< Structure used for bit access */ 109 uint32_t reg; /*!< Type used for register access */ 110 } ICM_SR_Type; 111 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 112 113 /* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */ 114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 115 typedef union { 116 struct { 117 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Enable */ 118 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Enable */ 119 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Enable */ 120 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition detected Interrupt Enable */ 121 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Enable */ 122 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */ 123 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Enable */ 124 uint32_t :7; /*!< bit: 25..31 Reserved */ 125 } bit; /*!< Structure used for bit access */ 126 uint32_t reg; /*!< Type used for register access */ 127 } ICM_IER_Type; 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 129 130 /* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */ 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 struct { 134 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Disable */ 135 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Disable */ 136 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Disable */ 137 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */ 138 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition detected Interrupt Disable */ 139 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */ 140 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Disable */ 141 uint32_t :7; /*!< bit: 25..31 Reserved */ 142 } bit; /*!< Structure used for bit access */ 143 uint32_t reg; /*!< Type used for register access */ 144 } ICM_IDR_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 /* -------- ICM_IMR : (ICM Offset: 0x18) ( R/ 32) Interrupt Mask -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Mask */ 152 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Mask */ 153 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Mask */ 154 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */ 155 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Mask */ 156 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Mask */ 157 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Mask */ 158 uint32_t :7; /*!< bit: 25..31 Reserved */ 159 } bit; /*!< Structure used for bit access */ 160 uint32_t reg; /*!< Type used for register access */ 161 } ICM_IMR_Type; 162 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 163 164 /* -------- ICM_ISR : (ICM Offset: 0x1C) ( R/ 32) Interrupt Status -------- */ 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 166 typedef union { 167 struct { 168 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed */ 169 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch */ 170 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error */ 171 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected */ 172 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected */ 173 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Detected */ 174 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Status */ 175 uint32_t :7; /*!< bit: 25..31 Reserved */ 176 } bit; /*!< Structure used for bit access */ 177 uint32_t reg; /*!< Type used for register access */ 178 } ICM_ISR_Type; 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 180 181 /* -------- ICM_UASR : (ICM Offset: 0x20) ( R/ 32) Undefined Access Status -------- */ 182 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 183 typedef union { 184 struct { 185 uint32_t URAT:3; /*!< bit: 0.. 2 Undefined Register Access Trace */ 186 uint32_t :29; /*!< bit: 3..31 Reserved */ 187 } bit; /*!< Structure used for bit access */ 188 uint32_t reg; /*!< Type used for register access */ 189 } ICM_UASR_Type; 190 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 191 192 /* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */ 193 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 194 typedef union { 195 struct { 196 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 197 uint32_t DASA:26; /*!< bit: 6..31 Descriptor Area Start Address */ 198 } bit; /*!< Structure used for bit access */ 199 uint32_t reg; /*!< Type used for register access */ 200 } ICM_DSCR_Type; 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 202 203 /* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */ 204 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 205 typedef union { 206 struct { 207 uint32_t :7; /*!< bit: 0.. 6 Reserved */ 208 uint32_t HASA:25; /*!< bit: 7..31 Hash Area Start Address */ 209 } bit; /*!< Structure used for bit access */ 210 uint32_t reg; /*!< Type used for register access */ 211 } ICM_HASH_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 /* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */ 215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 216 typedef union { 217 struct { 218 uint32_t VAL:32; /*!< bit: 0..31 Initial Hash Value */ 219 } bit; /*!< Structure used for bit access */ 220 uint32_t reg; /*!< Type used for register access */ 221 } ICM_UIHVAL_Type; 222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 223 224 /** \brief ICM Descriptor SRAM registers */ 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 226 typedef struct { 227 __IO ICM_RADDR_Type RADDR; /**< \brief Offset: 0x00 (R/W 32) Region Start Address */ 228 __IO ICM_RCFG_Type RCFG; /**< \brief Offset: 0x04 (R/W 32) Region Configuration */ 229 __IO ICM_RCTRL_Type RCTRL; /**< \brief Offset: 0x08 (R/W 32) Region Control */ 230 __IO ICM_RNEXT_Type RNEXT; /**< \brief Offset: 0x0C (R/W 32) Region Next Address */ 231 } IcmDescriptor; 232 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 233 234 /** \brief ICM APB hardware registers */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef struct { 237 __IO ICM_CFG_Type CFG; /**< \brief Offset: 0x00 (R/W 32) Configuration */ 238 __O ICM_CTRL_Type CTRL; /**< \brief Offset: 0x04 ( /W 32) Control */ 239 __I ICM_SR_Type SR; /**< \brief Offset: 0x08 (R/ 32) Status */ 240 RoReg8 Reserved1[0x4]; 241 __O ICM_IER_Type IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */ 242 __O ICM_IDR_Type IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */ 243 __I ICM_IMR_Type IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask */ 244 __I ICM_ISR_Type ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status */ 245 __I ICM_UASR_Type UASR; /**< \brief Offset: 0x20 (R/ 32) Undefined Access Status */ 246 RoReg8 Reserved2[0xC]; 247 __IO ICM_DSCR_Type DSCR; /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */ 248 __IO ICM_HASH_Type HASH; /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */ 249 __O ICM_UIHVAL_Type UIHVAL[8]; /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */ 250 } Icm; 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 253 #endif /* _MICROCHIP_PIC32CXSG_ICM_COMPONENT_FIXUP_H_ */ 254
