1 /* 2 * Component description for ICM 3 * 4 * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:59Z */ 21 #ifndef _PIC32CXSG61_ICM_COMPONENT_H_ 22 #define _PIC32CXSG61_ICM_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR ICM */ 26 /* ************************************************************************** */ 27 28 /* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */ 29 #define ICM_RADDR_Msk _UINT32_(0x00000000) /* (ICM_RADDR) Register Mask */ 30 31 32 /* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */ 33 #define ICM_RCFG_RESETVALUE _UINT32_(0x00) /* (ICM_RCFG) Region Configuration Reset Value */ 34 35 #define ICM_RCFG_CDWBN_Pos _UINT32_(0) /* (ICM_RCFG) Compare Digest Write Back Position */ 36 #define ICM_RCFG_CDWBN_Msk (_UINT32_(0x1) << ICM_RCFG_CDWBN_Pos) /* (ICM_RCFG) Compare Digest Write Back Mask */ 37 #define ICM_RCFG_CDWBN(value) (ICM_RCFG_CDWBN_Msk & (_UINT32_(value) << ICM_RCFG_CDWBN_Pos)) /* Assigment of value for CDWBN in the ICM_RCFG register */ 38 #define ICM_RCFG_CDWBN_WRBA_Val _UINT32_(0x0) /* (ICM_RCFG) */ 39 #define ICM_RCFG_CDWBN_COMP_Val _UINT32_(0x1) /* (ICM_RCFG) */ 40 #define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos) /* (ICM_RCFG) Position */ 41 #define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos) /* (ICM_RCFG) Position */ 42 #define ICM_RCFG_WRAP_Pos _UINT32_(1) /* (ICM_RCFG) Region Wrap Position */ 43 #define ICM_RCFG_WRAP_Msk (_UINT32_(0x1) << ICM_RCFG_WRAP_Pos) /* (ICM_RCFG) Region Wrap Mask */ 44 #define ICM_RCFG_WRAP(value) (ICM_RCFG_WRAP_Msk & (_UINT32_(value) << ICM_RCFG_WRAP_Pos)) /* Assigment of value for WRAP in the ICM_RCFG register */ 45 #define ICM_RCFG_WRAP_NO_Val _UINT32_(0x0) /* (ICM_RCFG) */ 46 #define ICM_RCFG_WRAP_YES_Val _UINT32_(0x1) /* (ICM_RCFG) */ 47 #define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos) /* (ICM_RCFG) Position */ 48 #define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos) /* (ICM_RCFG) Position */ 49 #define ICM_RCFG_EOM_Pos _UINT32_(2) /* (ICM_RCFG) End of Monitoring Position */ 50 #define ICM_RCFG_EOM_Msk (_UINT32_(0x1) << ICM_RCFG_EOM_Pos) /* (ICM_RCFG) End of Monitoring Mask */ 51 #define ICM_RCFG_EOM(value) (ICM_RCFG_EOM_Msk & (_UINT32_(value) << ICM_RCFG_EOM_Pos)) /* Assigment of value for EOM in the ICM_RCFG register */ 52 #define ICM_RCFG_EOM_NO_Val _UINT32_(0x0) /* (ICM_RCFG) */ 53 #define ICM_RCFG_EOM_YES_Val _UINT32_(0x1) /* (ICM_RCFG) */ 54 #define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos) /* (ICM_RCFG) Position */ 55 #define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos) /* (ICM_RCFG) Position */ 56 #define ICM_RCFG_RHIEN_Pos _UINT32_(4) /* (ICM_RCFG) Region Hash Interrupt Enable Position */ 57 #define ICM_RCFG_RHIEN_Msk (_UINT32_(0x1) << ICM_RCFG_RHIEN_Pos) /* (ICM_RCFG) Region Hash Interrupt Enable Mask */ 58 #define ICM_RCFG_RHIEN(value) (ICM_RCFG_RHIEN_Msk & (_UINT32_(value) << ICM_RCFG_RHIEN_Pos)) /* Assigment of value for RHIEN in the ICM_RCFG register */ 59 #define ICM_RCFG_RHIEN_EN_Val _UINT32_(0x0) /* (ICM_RCFG) */ 60 #define ICM_RCFG_RHIEN_DIS_Val _UINT32_(0x1) /* (ICM_RCFG) */ 61 #define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos) /* (ICM_RCFG) Position */ 62 #define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos) /* (ICM_RCFG) Position */ 63 #define ICM_RCFG_DMIEN_Pos _UINT32_(5) /* (ICM_RCFG) Region Digest Mismatch Interrupt Enable Position */ 64 #define ICM_RCFG_DMIEN_Msk (_UINT32_(0x1) << ICM_RCFG_DMIEN_Pos) /* (ICM_RCFG) Region Digest Mismatch Interrupt Enable Mask */ 65 #define ICM_RCFG_DMIEN(value) (ICM_RCFG_DMIEN_Msk & (_UINT32_(value) << ICM_RCFG_DMIEN_Pos)) /* Assigment of value for DMIEN in the ICM_RCFG register */ 66 #define ICM_RCFG_DMIEN_EN_Val _UINT32_(0x0) /* (ICM_RCFG) */ 67 #define ICM_RCFG_DMIEN_DIS_Val _UINT32_(0x1) /* (ICM_RCFG) */ 68 #define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos) /* (ICM_RCFG) Position */ 69 #define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos) /* (ICM_RCFG) Position */ 70 #define ICM_RCFG_BEIEN_Pos _UINT32_(6) /* (ICM_RCFG) Region Bus Error Interrupt Enable Position */ 71 #define ICM_RCFG_BEIEN_Msk (_UINT32_(0x1) << ICM_RCFG_BEIEN_Pos) /* (ICM_RCFG) Region Bus Error Interrupt Enable Mask */ 72 #define ICM_RCFG_BEIEN(value) (ICM_RCFG_BEIEN_Msk & (_UINT32_(value) << ICM_RCFG_BEIEN_Pos)) /* Assigment of value for BEIEN in the ICM_RCFG register */ 73 #define ICM_RCFG_BEIEN_EN_Val _UINT32_(0x0) /* (ICM_RCFG) */ 74 #define ICM_RCFG_BEIEN_DIS_Val _UINT32_(0x1) /* (ICM_RCFG) */ 75 #define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos) /* (ICM_RCFG) Position */ 76 #define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos) /* (ICM_RCFG) Position */ 77 #define ICM_RCFG_WCIEN_Pos _UINT32_(7) /* (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable Position */ 78 #define ICM_RCFG_WCIEN_Msk (_UINT32_(0x1) << ICM_RCFG_WCIEN_Pos) /* (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable Mask */ 79 #define ICM_RCFG_WCIEN(value) (ICM_RCFG_WCIEN_Msk & (_UINT32_(value) << ICM_RCFG_WCIEN_Pos)) /* Assigment of value for WCIEN in the ICM_RCFG register */ 80 #define ICM_RCFG_WCIEN_EN_Val _UINT32_(0x0) /* (ICM_RCFG) */ 81 #define ICM_RCFG_WCIEN_DIS_Val _UINT32_(0x1) /* (ICM_RCFG) */ 82 #define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos) /* (ICM_RCFG) Position */ 83 #define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos) /* (ICM_RCFG) Position */ 84 #define ICM_RCFG_ECIEN_Pos _UINT32_(8) /* (ICM_RCFG) Region End bit Condition detected Interrupt Enable Position */ 85 #define ICM_RCFG_ECIEN_Msk (_UINT32_(0x1) << ICM_RCFG_ECIEN_Pos) /* (ICM_RCFG) Region End bit Condition detected Interrupt Enable Mask */ 86 #define ICM_RCFG_ECIEN(value) (ICM_RCFG_ECIEN_Msk & (_UINT32_(value) << ICM_RCFG_ECIEN_Pos)) /* Assigment of value for ECIEN in the ICM_RCFG register */ 87 #define ICM_RCFG_ECIEN_EN_Val _UINT32_(0x0) /* (ICM_RCFG) */ 88 #define ICM_RCFG_ECIEN_DIS_Val _UINT32_(0x1) /* (ICM_RCFG) */ 89 #define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos) /* (ICM_RCFG) Position */ 90 #define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos) /* (ICM_RCFG) Position */ 91 #define ICM_RCFG_SUIEN_Pos _UINT32_(9) /* (ICM_RCFG) Region Status Updated Interrupt Enable Position */ 92 #define ICM_RCFG_SUIEN_Msk (_UINT32_(0x1) << ICM_RCFG_SUIEN_Pos) /* (ICM_RCFG) Region Status Updated Interrupt Enable Mask */ 93 #define ICM_RCFG_SUIEN(value) (ICM_RCFG_SUIEN_Msk & (_UINT32_(value) << ICM_RCFG_SUIEN_Pos)) /* Assigment of value for SUIEN in the ICM_RCFG register */ 94 #define ICM_RCFG_SUIEN_EN_Val _UINT32_(0x0) /* (ICM_RCFG) */ 95 #define ICM_RCFG_SUIEN_DIS_Val _UINT32_(0x1) /* (ICM_RCFG) */ 96 #define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos) /* (ICM_RCFG) Position */ 97 #define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos) /* (ICM_RCFG) Position */ 98 #define ICM_RCFG_PROCDLY_Pos _UINT32_(10) /* (ICM_RCFG) SHA Processing Delay Position */ 99 #define ICM_RCFG_PROCDLY_Msk (_UINT32_(0x1) << ICM_RCFG_PROCDLY_Pos) /* (ICM_RCFG) SHA Processing Delay Mask */ 100 #define ICM_RCFG_PROCDLY(value) (ICM_RCFG_PROCDLY_Msk & (_UINT32_(value) << ICM_RCFG_PROCDLY_Pos)) /* Assigment of value for PROCDLY in the ICM_RCFG register */ 101 #define ICM_RCFG_PROCDLY_SHORT_Val _UINT32_(0x0) /* (ICM_RCFG) */ 102 #define ICM_RCFG_PROCDLY_LONG_Val _UINT32_(0x1) /* (ICM_RCFG) */ 103 #define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos) /* (ICM_RCFG) Position */ 104 #define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos) /* (ICM_RCFG) Position */ 105 #define ICM_RCFG_ALGO_Pos _UINT32_(12) /* (ICM_RCFG) SHA Algorithm Position */ 106 #define ICM_RCFG_ALGO_Msk (_UINT32_(0x7) << ICM_RCFG_ALGO_Pos) /* (ICM_RCFG) SHA Algorithm Mask */ 107 #define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & (_UINT32_(value) << ICM_RCFG_ALGO_Pos)) /* Assigment of value for ALGO in the ICM_RCFG register */ 108 #define ICM_RCFG_MRPROT_Pos _UINT32_(24) /* (ICM_RCFG) Memory Region AHB Protection Position */ 109 #define ICM_RCFG_MRPROT_Msk (_UINT32_(0x3F) << ICM_RCFG_MRPROT_Pos) /* (ICM_RCFG) Memory Region AHB Protection Mask */ 110 #define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & (_UINT32_(value) << ICM_RCFG_MRPROT_Pos)) /* Assigment of value for MRPROT in the ICM_RCFG register */ 111 #define ICM_RCFG_Msk _UINT32_(0x3F0077F7) /* (ICM_RCFG) Register Mask */ 112 113 114 /* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */ 115 #define ICM_RCTRL_TRSIZE_Pos _UINT32_(0) /* (ICM_RCTRL) Transfer Size Position */ 116 #define ICM_RCTRL_TRSIZE_Msk (_UINT32_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos) /* (ICM_RCTRL) Transfer Size Mask */ 117 #define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & (_UINT32_(value) << ICM_RCTRL_TRSIZE_Pos)) /* Assigment of value for TRSIZE in the ICM_RCTRL register */ 118 #define ICM_RCTRL_Msk _UINT32_(0x0000FFFF) /* (ICM_RCTRL) Register Mask */ 119 120 121 /* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */ 122 #define ICM_RNEXT_Msk _UINT32_(0x00000000) /* (ICM_RNEXT) Register Mask */ 123 124 125 /* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */ 126 #define ICM_CFG_RESETVALUE _UINT32_(0x00) /* (ICM_CFG) Configuration Reset Value */ 127 128 #define ICM_CFG_WBDIS_Pos _UINT32_(0) /* (ICM_CFG) Write Back Disable Position */ 129 #define ICM_CFG_WBDIS_Msk (_UINT32_(0x1) << ICM_CFG_WBDIS_Pos) /* (ICM_CFG) Write Back Disable Mask */ 130 #define ICM_CFG_WBDIS(value) (ICM_CFG_WBDIS_Msk & (_UINT32_(value) << ICM_CFG_WBDIS_Pos)) /* Assigment of value for WBDIS in the ICM_CFG register */ 131 #define ICM_CFG_EOMDIS_Pos _UINT32_(1) /* (ICM_CFG) End of Monitoring Disable Position */ 132 #define ICM_CFG_EOMDIS_Msk (_UINT32_(0x1) << ICM_CFG_EOMDIS_Pos) /* (ICM_CFG) End of Monitoring Disable Mask */ 133 #define ICM_CFG_EOMDIS(value) (ICM_CFG_EOMDIS_Msk & (_UINT32_(value) << ICM_CFG_EOMDIS_Pos)) /* Assigment of value for EOMDIS in the ICM_CFG register */ 134 #define ICM_CFG_SLBDIS_Pos _UINT32_(2) /* (ICM_CFG) Secondary List Branching Disable Position */ 135 #define ICM_CFG_SLBDIS_Msk (_UINT32_(0x1) << ICM_CFG_SLBDIS_Pos) /* (ICM_CFG) Secondary List Branching Disable Mask */ 136 #define ICM_CFG_SLBDIS(value) (ICM_CFG_SLBDIS_Msk & (_UINT32_(value) << ICM_CFG_SLBDIS_Pos)) /* Assigment of value for SLBDIS in the ICM_CFG register */ 137 #define ICM_CFG_BBC_Pos _UINT32_(4) /* (ICM_CFG) Bus Burden Control Position */ 138 #define ICM_CFG_BBC_Msk (_UINT32_(0xF) << ICM_CFG_BBC_Pos) /* (ICM_CFG) Bus Burden Control Mask */ 139 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & (_UINT32_(value) << ICM_CFG_BBC_Pos)) /* Assigment of value for BBC in the ICM_CFG register */ 140 #define ICM_CFG_ASCD_Pos _UINT32_(8) /* (ICM_CFG) Automatic Switch To Compare Digest Position */ 141 #define ICM_CFG_ASCD_Msk (_UINT32_(0x1) << ICM_CFG_ASCD_Pos) /* (ICM_CFG) Automatic Switch To Compare Digest Mask */ 142 #define ICM_CFG_ASCD(value) (ICM_CFG_ASCD_Msk & (_UINT32_(value) << ICM_CFG_ASCD_Pos)) /* Assigment of value for ASCD in the ICM_CFG register */ 143 #define ICM_CFG_DUALBUFF_Pos _UINT32_(9) /* (ICM_CFG) Dual Input Buffer Position */ 144 #define ICM_CFG_DUALBUFF_Msk (_UINT32_(0x1) << ICM_CFG_DUALBUFF_Pos) /* (ICM_CFG) Dual Input Buffer Mask */ 145 #define ICM_CFG_DUALBUFF(value) (ICM_CFG_DUALBUFF_Msk & (_UINT32_(value) << ICM_CFG_DUALBUFF_Pos)) /* Assigment of value for DUALBUFF in the ICM_CFG register */ 146 #define ICM_CFG_UIHASH_Pos _UINT32_(12) /* (ICM_CFG) User Initial Hash Value Position */ 147 #define ICM_CFG_UIHASH_Msk (_UINT32_(0x1) << ICM_CFG_UIHASH_Pos) /* (ICM_CFG) User Initial Hash Value Mask */ 148 #define ICM_CFG_UIHASH(value) (ICM_CFG_UIHASH_Msk & (_UINT32_(value) << ICM_CFG_UIHASH_Pos)) /* Assigment of value for UIHASH in the ICM_CFG register */ 149 #define ICM_CFG_UALGO_Pos _UINT32_(13) /* (ICM_CFG) User SHA Algorithm Position */ 150 #define ICM_CFG_UALGO_Msk (_UINT32_(0x7) << ICM_CFG_UALGO_Pos) /* (ICM_CFG) User SHA Algorithm Mask */ 151 #define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & (_UINT32_(value) << ICM_CFG_UALGO_Pos)) /* Assigment of value for UALGO in the ICM_CFG register */ 152 #define ICM_CFG_UALGO_SHA1_Val _UINT32_(0x0) /* (ICM_CFG) SHA1 Algorithm */ 153 #define ICM_CFG_UALGO_SHA256_Val _UINT32_(0x1) /* (ICM_CFG) SHA256 Algorithm */ 154 #define ICM_CFG_UALGO_SHA224_Val _UINT32_(0x4) /* (ICM_CFG) SHA224 Algorithm */ 155 #define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /* (ICM_CFG) SHA1 Algorithm Position */ 156 #define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /* (ICM_CFG) SHA256 Algorithm Position */ 157 #define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /* (ICM_CFG) SHA224 Algorithm Position */ 158 #define ICM_CFG_Msk _UINT32_(0x0000F3F7) /* (ICM_CFG) Register Mask */ 159 160 161 /* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */ 162 #define ICM_CTRL_ENABLE_Pos _UINT32_(0) /* (ICM_CTRL) ICM Enable Position */ 163 #define ICM_CTRL_ENABLE_Msk (_UINT32_(0x1) << ICM_CTRL_ENABLE_Pos) /* (ICM_CTRL) ICM Enable Mask */ 164 #define ICM_CTRL_ENABLE(value) (ICM_CTRL_ENABLE_Msk & (_UINT32_(value) << ICM_CTRL_ENABLE_Pos)) /* Assigment of value for ENABLE in the ICM_CTRL register */ 165 #define ICM_CTRL_DISABLE_Pos _UINT32_(1) /* (ICM_CTRL) ICM Disable Register Position */ 166 #define ICM_CTRL_DISABLE_Msk (_UINT32_(0x1) << ICM_CTRL_DISABLE_Pos) /* (ICM_CTRL) ICM Disable Register Mask */ 167 #define ICM_CTRL_DISABLE(value) (ICM_CTRL_DISABLE_Msk & (_UINT32_(value) << ICM_CTRL_DISABLE_Pos)) /* Assigment of value for DISABLE in the ICM_CTRL register */ 168 #define ICM_CTRL_SWRST_Pos _UINT32_(2) /* (ICM_CTRL) Software Reset Position */ 169 #define ICM_CTRL_SWRST_Msk (_UINT32_(0x1) << ICM_CTRL_SWRST_Pos) /* (ICM_CTRL) Software Reset Mask */ 170 #define ICM_CTRL_SWRST(value) (ICM_CTRL_SWRST_Msk & (_UINT32_(value) << ICM_CTRL_SWRST_Pos)) /* Assigment of value for SWRST in the ICM_CTRL register */ 171 #define ICM_CTRL_REHASH_Pos _UINT32_(4) /* (ICM_CTRL) Recompute Internal Hash Position */ 172 #define ICM_CTRL_REHASH_Msk (_UINT32_(0xF) << ICM_CTRL_REHASH_Pos) /* (ICM_CTRL) Recompute Internal Hash Mask */ 173 #define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & (_UINT32_(value) << ICM_CTRL_REHASH_Pos)) /* Assigment of value for REHASH in the ICM_CTRL register */ 174 #define ICM_CTRL_RMDIS_Pos _UINT32_(8) /* (ICM_CTRL) Region Monitoring Disable Position */ 175 #define ICM_CTRL_RMDIS_Msk (_UINT32_(0xF) << ICM_CTRL_RMDIS_Pos) /* (ICM_CTRL) Region Monitoring Disable Mask */ 176 #define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & (_UINT32_(value) << ICM_CTRL_RMDIS_Pos)) /* Assigment of value for RMDIS in the ICM_CTRL register */ 177 #define ICM_CTRL_RMEN_Pos _UINT32_(12) /* (ICM_CTRL) Region Monitoring Enable Position */ 178 #define ICM_CTRL_RMEN_Msk (_UINT32_(0xF) << ICM_CTRL_RMEN_Pos) /* (ICM_CTRL) Region Monitoring Enable Mask */ 179 #define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & (_UINT32_(value) << ICM_CTRL_RMEN_Pos)) /* Assigment of value for RMEN in the ICM_CTRL register */ 180 #define ICM_CTRL_Msk _UINT32_(0x0000FFF7) /* (ICM_CTRL) Register Mask */ 181 182 183 /* -------- ICM_SR : (ICM Offset: 0x08) ( R/ 32) Status -------- */ 184 #define ICM_SR_RESETVALUE _UINT32_(0x00) /* (ICM_SR) Status Reset Value */ 185 186 #define ICM_SR_ENABLE_Pos _UINT32_(0) /* (ICM_SR) ICM Controller Enable Register Position */ 187 #define ICM_SR_ENABLE_Msk (_UINT32_(0x1) << ICM_SR_ENABLE_Pos) /* (ICM_SR) ICM Controller Enable Register Mask */ 188 #define ICM_SR_ENABLE(value) (ICM_SR_ENABLE_Msk & (_UINT32_(value) << ICM_SR_ENABLE_Pos)) /* Assigment of value for ENABLE in the ICM_SR register */ 189 #define ICM_SR_RAWRMDIS_Pos _UINT32_(8) /* (ICM_SR) RAW Region Monitoring Disabled Status Position */ 190 #define ICM_SR_RAWRMDIS_Msk (_UINT32_(0xF) << ICM_SR_RAWRMDIS_Pos) /* (ICM_SR) RAW Region Monitoring Disabled Status Mask */ 191 #define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & (_UINT32_(value) << ICM_SR_RAWRMDIS_Pos)) /* Assigment of value for RAWRMDIS in the ICM_SR register */ 192 #define ICM_SR_RMDIS_Pos _UINT32_(12) /* (ICM_SR) Region Monitoring Disabled Status Position */ 193 #define ICM_SR_RMDIS_Msk (_UINT32_(0xF) << ICM_SR_RMDIS_Pos) /* (ICM_SR) Region Monitoring Disabled Status Mask */ 194 #define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & (_UINT32_(value) << ICM_SR_RMDIS_Pos)) /* Assigment of value for RMDIS in the ICM_SR register */ 195 #define ICM_SR_Msk _UINT32_(0x0000FF01) /* (ICM_SR) Register Mask */ 196 197 198 /* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */ 199 #define ICM_IER_RHC_Pos _UINT32_(0) /* (ICM_IER) Region Hash Completed Interrupt Enable Position */ 200 #define ICM_IER_RHC_Msk (_UINT32_(0xF) << ICM_IER_RHC_Pos) /* (ICM_IER) Region Hash Completed Interrupt Enable Mask */ 201 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & (_UINT32_(value) << ICM_IER_RHC_Pos)) /* Assigment of value for RHC in the ICM_IER register */ 202 #define ICM_IER_RDM_Pos _UINT32_(4) /* (ICM_IER) Region Digest Mismatch Interrupt Enable Position */ 203 #define ICM_IER_RDM_Msk (_UINT32_(0xF) << ICM_IER_RDM_Pos) /* (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */ 204 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & (_UINT32_(value) << ICM_IER_RDM_Pos)) /* Assigment of value for RDM in the ICM_IER register */ 205 #define ICM_IER_RBE_Pos _UINT32_(8) /* (ICM_IER) Region Bus Error Interrupt Enable Position */ 206 #define ICM_IER_RBE_Msk (_UINT32_(0xF) << ICM_IER_RBE_Pos) /* (ICM_IER) Region Bus Error Interrupt Enable Mask */ 207 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & (_UINT32_(value) << ICM_IER_RBE_Pos)) /* Assigment of value for RBE in the ICM_IER register */ 208 #define ICM_IER_RWC_Pos _UINT32_(12) /* (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */ 209 #define ICM_IER_RWC_Msk (_UINT32_(0xF) << ICM_IER_RWC_Pos) /* (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */ 210 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & (_UINT32_(value) << ICM_IER_RWC_Pos)) /* Assigment of value for RWC in the ICM_IER register */ 211 #define ICM_IER_REC_Pos _UINT32_(16) /* (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */ 212 #define ICM_IER_REC_Msk (_UINT32_(0xF) << ICM_IER_REC_Pos) /* (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */ 213 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & (_UINT32_(value) << ICM_IER_REC_Pos)) /* Assigment of value for REC in the ICM_IER register */ 214 #define ICM_IER_RSU_Pos _UINT32_(20) /* (ICM_IER) Region Status Updated Interrupt Disable Position */ 215 #define ICM_IER_RSU_Msk (_UINT32_(0xF) << ICM_IER_RSU_Pos) /* (ICM_IER) Region Status Updated Interrupt Disable Mask */ 216 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & (_UINT32_(value) << ICM_IER_RSU_Pos)) /* Assigment of value for RSU in the ICM_IER register */ 217 #define ICM_IER_URAD_Pos _UINT32_(24) /* (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */ 218 #define ICM_IER_URAD_Msk (_UINT32_(0x1) << ICM_IER_URAD_Pos) /* (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */ 219 #define ICM_IER_URAD(value) (ICM_IER_URAD_Msk & (_UINT32_(value) << ICM_IER_URAD_Pos)) /* Assigment of value for URAD in the ICM_IER register */ 220 #define ICM_IER_Msk _UINT32_(0x01FFFFFF) /* (ICM_IER) Register Mask */ 221 222 223 /* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */ 224 #define ICM_IDR_RESETVALUE _UINT32_(0x00) /* (ICM_IDR) Interrupt Disable Reset Value */ 225 226 #define ICM_IDR_RHC_Pos _UINT32_(0) /* (ICM_IDR) Region Hash Completed Interrupt Disable Position */ 227 #define ICM_IDR_RHC_Msk (_UINT32_(0xF) << ICM_IDR_RHC_Pos) /* (ICM_IDR) Region Hash Completed Interrupt Disable Mask */ 228 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & (_UINT32_(value) << ICM_IDR_RHC_Pos)) /* Assigment of value for RHC in the ICM_IDR register */ 229 #define ICM_IDR_RDM_Pos _UINT32_(4) /* (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */ 230 #define ICM_IDR_RDM_Msk (_UINT32_(0xF) << ICM_IDR_RDM_Pos) /* (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */ 231 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & (_UINT32_(value) << ICM_IDR_RDM_Pos)) /* Assigment of value for RDM in the ICM_IDR register */ 232 #define ICM_IDR_RBE_Pos _UINT32_(8) /* (ICM_IDR) Region Bus Error Interrupt Disable Position */ 233 #define ICM_IDR_RBE_Msk (_UINT32_(0xF) << ICM_IDR_RBE_Pos) /* (ICM_IDR) Region Bus Error Interrupt Disable Mask */ 234 #define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & (_UINT32_(value) << ICM_IDR_RBE_Pos)) /* Assigment of value for RBE in the ICM_IDR register */ 235 #define ICM_IDR_RWC_Pos _UINT32_(12) /* (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */ 236 #define ICM_IDR_RWC_Msk (_UINT32_(0xF) << ICM_IDR_RWC_Pos) /* (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */ 237 #define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & (_UINT32_(value) << ICM_IDR_RWC_Pos)) /* Assigment of value for RWC in the ICM_IDR register */ 238 #define ICM_IDR_REC_Pos _UINT32_(16) /* (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */ 239 #define ICM_IDR_REC_Msk (_UINT32_(0xF) << ICM_IDR_REC_Pos) /* (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */ 240 #define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & (_UINT32_(value) << ICM_IDR_REC_Pos)) /* Assigment of value for REC in the ICM_IDR register */ 241 #define ICM_IDR_RSU_Pos _UINT32_(20) /* (ICM_IDR) Region Status Updated Interrupt Disable Position */ 242 #define ICM_IDR_RSU_Msk (_UINT32_(0xF) << ICM_IDR_RSU_Pos) /* (ICM_IDR) Region Status Updated Interrupt Disable Mask */ 243 #define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & (_UINT32_(value) << ICM_IDR_RSU_Pos)) /* Assigment of value for RSU in the ICM_IDR register */ 244 #define ICM_IDR_URAD_Pos _UINT32_(24) /* (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */ 245 #define ICM_IDR_URAD_Msk (_UINT32_(0x1) << ICM_IDR_URAD_Pos) /* (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */ 246 #define ICM_IDR_URAD(value) (ICM_IDR_URAD_Msk & (_UINT32_(value) << ICM_IDR_URAD_Pos)) /* Assigment of value for URAD in the ICM_IDR register */ 247 #define ICM_IDR_Msk _UINT32_(0x01FFFFFF) /* (ICM_IDR) Register Mask */ 248 249 250 /* -------- ICM_IMR : (ICM Offset: 0x18) ( R/ 32) Interrupt Mask -------- */ 251 #define ICM_IMR_RESETVALUE _UINT32_(0x00) /* (ICM_IMR) Interrupt Mask Reset Value */ 252 253 #define ICM_IMR_RHC_Pos _UINT32_(0) /* (ICM_IMR) Region Hash Completed Interrupt Mask Position */ 254 #define ICM_IMR_RHC_Msk (_UINT32_(0xF) << ICM_IMR_RHC_Pos) /* (ICM_IMR) Region Hash Completed Interrupt Mask Mask */ 255 #define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & (_UINT32_(value) << ICM_IMR_RHC_Pos)) /* Assigment of value for RHC in the ICM_IMR register */ 256 #define ICM_IMR_RDM_Pos _UINT32_(4) /* (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */ 257 #define ICM_IMR_RDM_Msk (_UINT32_(0xF) << ICM_IMR_RDM_Pos) /* (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */ 258 #define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & (_UINT32_(value) << ICM_IMR_RDM_Pos)) /* Assigment of value for RDM in the ICM_IMR register */ 259 #define ICM_IMR_RBE_Pos _UINT32_(8) /* (ICM_IMR) Region Bus Error Interrupt Mask Position */ 260 #define ICM_IMR_RBE_Msk (_UINT32_(0xF) << ICM_IMR_RBE_Pos) /* (ICM_IMR) Region Bus Error Interrupt Mask Mask */ 261 #define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & (_UINT32_(value) << ICM_IMR_RBE_Pos)) /* Assigment of value for RBE in the ICM_IMR register */ 262 #define ICM_IMR_RWC_Pos _UINT32_(12) /* (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */ 263 #define ICM_IMR_RWC_Msk (_UINT32_(0xF) << ICM_IMR_RWC_Pos) /* (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */ 264 #define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & (_UINT32_(value) << ICM_IMR_RWC_Pos)) /* Assigment of value for RWC in the ICM_IMR register */ 265 #define ICM_IMR_REC_Pos _UINT32_(16) /* (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */ 266 #define ICM_IMR_REC_Msk (_UINT32_(0xF) << ICM_IMR_REC_Pos) /* (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */ 267 #define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & (_UINT32_(value) << ICM_IMR_REC_Pos)) /* Assigment of value for REC in the ICM_IMR register */ 268 #define ICM_IMR_RSU_Pos _UINT32_(20) /* (ICM_IMR) Region Status Updated Interrupt Mask Position */ 269 #define ICM_IMR_RSU_Msk (_UINT32_(0xF) << ICM_IMR_RSU_Pos) /* (ICM_IMR) Region Status Updated Interrupt Mask Mask */ 270 #define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & (_UINT32_(value) << ICM_IMR_RSU_Pos)) /* Assigment of value for RSU in the ICM_IMR register */ 271 #define ICM_IMR_URAD_Pos _UINT32_(24) /* (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */ 272 #define ICM_IMR_URAD_Msk (_UINT32_(0x1) << ICM_IMR_URAD_Pos) /* (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */ 273 #define ICM_IMR_URAD(value) (ICM_IMR_URAD_Msk & (_UINT32_(value) << ICM_IMR_URAD_Pos)) /* Assigment of value for URAD in the ICM_IMR register */ 274 #define ICM_IMR_Msk _UINT32_(0x01FFFFFF) /* (ICM_IMR) Register Mask */ 275 276 277 /* -------- ICM_ISR : (ICM Offset: 0x1C) ( R/ 32) Interrupt Status -------- */ 278 #define ICM_ISR_RESETVALUE _UINT32_(0x00) /* (ICM_ISR) Interrupt Status Reset Value */ 279 280 #define ICM_ISR_RHC_Pos _UINT32_(0) /* (ICM_ISR) Region Hash Completed Position */ 281 #define ICM_ISR_RHC_Msk (_UINT32_(0xF) << ICM_ISR_RHC_Pos) /* (ICM_ISR) Region Hash Completed Mask */ 282 #define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & (_UINT32_(value) << ICM_ISR_RHC_Pos)) /* Assigment of value for RHC in the ICM_ISR register */ 283 #define ICM_ISR_RDM_Pos _UINT32_(4) /* (ICM_ISR) Region Digest Mismatch Position */ 284 #define ICM_ISR_RDM_Msk (_UINT32_(0xF) << ICM_ISR_RDM_Pos) /* (ICM_ISR) Region Digest Mismatch Mask */ 285 #define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & (_UINT32_(value) << ICM_ISR_RDM_Pos)) /* Assigment of value for RDM in the ICM_ISR register */ 286 #define ICM_ISR_RBE_Pos _UINT32_(8) /* (ICM_ISR) Region Bus Error Position */ 287 #define ICM_ISR_RBE_Msk (_UINT32_(0xF) << ICM_ISR_RBE_Pos) /* (ICM_ISR) Region Bus Error Mask */ 288 #define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & (_UINT32_(value) << ICM_ISR_RBE_Pos)) /* Assigment of value for RBE in the ICM_ISR register */ 289 #define ICM_ISR_RWC_Pos _UINT32_(12) /* (ICM_ISR) Region Wrap Condition Detected Position */ 290 #define ICM_ISR_RWC_Msk (_UINT32_(0xF) << ICM_ISR_RWC_Pos) /* (ICM_ISR) Region Wrap Condition Detected Mask */ 291 #define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & (_UINT32_(value) << ICM_ISR_RWC_Pos)) /* Assigment of value for RWC in the ICM_ISR register */ 292 #define ICM_ISR_REC_Pos _UINT32_(16) /* (ICM_ISR) Region End bit Condition Detected Position */ 293 #define ICM_ISR_REC_Msk (_UINT32_(0xF) << ICM_ISR_REC_Pos) /* (ICM_ISR) Region End bit Condition Detected Mask */ 294 #define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & (_UINT32_(value) << ICM_ISR_REC_Pos)) /* Assigment of value for REC in the ICM_ISR register */ 295 #define ICM_ISR_RSU_Pos _UINT32_(20) /* (ICM_ISR) Region Status Updated Detected Position */ 296 #define ICM_ISR_RSU_Msk (_UINT32_(0xF) << ICM_ISR_RSU_Pos) /* (ICM_ISR) Region Status Updated Detected Mask */ 297 #define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & (_UINT32_(value) << ICM_ISR_RSU_Pos)) /* Assigment of value for RSU in the ICM_ISR register */ 298 #define ICM_ISR_URAD_Pos _UINT32_(24) /* (ICM_ISR) Undefined Register Access Detection Status Position */ 299 #define ICM_ISR_URAD_Msk (_UINT32_(0x1) << ICM_ISR_URAD_Pos) /* (ICM_ISR) Undefined Register Access Detection Status Mask */ 300 #define ICM_ISR_URAD(value) (ICM_ISR_URAD_Msk & (_UINT32_(value) << ICM_ISR_URAD_Pos)) /* Assigment of value for URAD in the ICM_ISR register */ 301 #define ICM_ISR_Msk _UINT32_(0x01FFFFFF) /* (ICM_ISR) Register Mask */ 302 303 304 /* -------- ICM_UASR : (ICM Offset: 0x20) ( R/ 32) Undefined Access Status -------- */ 305 #define ICM_UASR_RESETVALUE _UINT32_(0x00) /* (ICM_UASR) Undefined Access Status Reset Value */ 306 307 #define ICM_UASR_URAT_Pos _UINT32_(0) /* (ICM_UASR) Undefined Register Access Trace Position */ 308 #define ICM_UASR_URAT_Msk (_UINT32_(0x7) << ICM_UASR_URAT_Pos) /* (ICM_UASR) Undefined Register Access Trace Mask */ 309 #define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & (_UINT32_(value) << ICM_UASR_URAT_Pos)) /* Assigment of value for URAT in the ICM_UASR register */ 310 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _UINT32_(0x0) /* (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */ 311 #define ICM_UASR_URAT_CFG_MODIFIED_Val _UINT32_(0x1) /* (ICM_UASR) CFG modified during active monitoring */ 312 #define ICM_UASR_URAT_DSCR_MODIFIED_Val _UINT32_(0x2) /* (ICM_UASR) DSCR modified during active monitoring */ 313 #define ICM_UASR_URAT_HASH_MODIFIED_Val _UINT32_(0x3) /* (ICM_UASR) HASH modified during active monitoring */ 314 #define ICM_UASR_URAT_READ_ACCESS_Val _UINT32_(0x4) /* (ICM_UASR) Write-only register read access */ 315 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /* (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded Position */ 316 #define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /* (ICM_UASR) CFG modified during active monitoring Position */ 317 #define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /* (ICM_UASR) DSCR modified during active monitoring Position */ 318 #define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /* (ICM_UASR) HASH modified during active monitoring Position */ 319 #define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /* (ICM_UASR) Write-only register read access Position */ 320 #define ICM_UASR_Msk _UINT32_(0x00000007) /* (ICM_UASR) Register Mask */ 321 322 323 /* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */ 324 #define ICM_DSCR_RESETVALUE _UINT32_(0x00) /* (ICM_DSCR) Region Descriptor Area Start Address Reset Value */ 325 326 #define ICM_DSCR_DASA_Pos _UINT32_(6) /* (ICM_DSCR) Descriptor Area Start Address Position */ 327 #define ICM_DSCR_DASA_Msk (_UINT32_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /* (ICM_DSCR) Descriptor Area Start Address Mask */ 328 #define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & (_UINT32_(value) << ICM_DSCR_DASA_Pos)) /* Assigment of value for DASA in the ICM_DSCR register */ 329 #define ICM_DSCR_Msk _UINT32_(0xFFFFFFC0) /* (ICM_DSCR) Register Mask */ 330 331 332 /* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */ 333 #define ICM_HASH_RESETVALUE _UINT32_(0x00) /* (ICM_HASH) Region Hash Area Start Address Reset Value */ 334 335 #define ICM_HASH_HASA_Pos _UINT32_(7) /* (ICM_HASH) Hash Area Start Address Position */ 336 #define ICM_HASH_HASA_Msk (_UINT32_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /* (ICM_HASH) Hash Area Start Address Mask */ 337 #define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & (_UINT32_(value) << ICM_HASH_HASA_Pos)) /* Assigment of value for HASA in the ICM_HASH register */ 338 #define ICM_HASH_Msk _UINT32_(0xFFFFFF80) /* (ICM_HASH) Register Mask */ 339 340 341 /* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */ 342 #define ICM_UIHVAL_RESETVALUE _UINT32_(0x00) /* (ICM_UIHVAL) User Initial Hash Value n Reset Value */ 343 344 #define ICM_UIHVAL_VAL_Pos _UINT32_(0) /* (ICM_UIHVAL) Initial Hash Value Position */ 345 #define ICM_UIHVAL_VAL_Msk (_UINT32_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /* (ICM_UIHVAL) Initial Hash Value Mask */ 346 #define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & (_UINT32_(value) << ICM_UIHVAL_VAL_Pos)) /* Assigment of value for VAL in the ICM_UIHVAL register */ 347 #define ICM_UIHVAL_Msk _UINT32_(0xFFFFFFFF) /* (ICM_UIHVAL) Register Mask */ 348 349 350 /** \brief ICM register offsets definitions */ 351 #define ICM_RADDR_REG_OFST _UINT32_(0x00) /* (ICM_RADDR) Region Start Address Offset */ 352 #define ICM_RCFG_REG_OFST _UINT32_(0x04) /* (ICM_RCFG) Region Configuration Offset */ 353 #define ICM_RCTRL_REG_OFST _UINT32_(0x08) /* (ICM_RCTRL) Region Control Offset */ 354 #define ICM_RNEXT_REG_OFST _UINT32_(0x0C) /* (ICM_RNEXT) Region Next Address Offset */ 355 #define ICM_CFG_REG_OFST _UINT32_(0x00) /* (ICM_CFG) Configuration Offset */ 356 #define ICM_CTRL_REG_OFST _UINT32_(0x04) /* (ICM_CTRL) Control Offset */ 357 #define ICM_SR_REG_OFST _UINT32_(0x08) /* (ICM_SR) Status Offset */ 358 #define ICM_IER_REG_OFST _UINT32_(0x10) /* (ICM_IER) Interrupt Enable Offset */ 359 #define ICM_IDR_REG_OFST _UINT32_(0x14) /* (ICM_IDR) Interrupt Disable Offset */ 360 #define ICM_IMR_REG_OFST _UINT32_(0x18) /* (ICM_IMR) Interrupt Mask Offset */ 361 #define ICM_ISR_REG_OFST _UINT32_(0x1C) /* (ICM_ISR) Interrupt Status Offset */ 362 #define ICM_UASR_REG_OFST _UINT32_(0x20) /* (ICM_UASR) Undefined Access Status Offset */ 363 #define ICM_DSCR_REG_OFST _UINT32_(0x30) /* (ICM_DSCR) Region Descriptor Area Start Address Offset */ 364 #define ICM_HASH_REG_OFST _UINT32_(0x34) /* (ICM_HASH) Region Hash Area Start Address Offset */ 365 #define ICM_UIHVAL_REG_OFST _UINT32_(0x38) /* (ICM_UIHVAL) User Initial Hash Value n Offset */ 366 #define ICM_UIHVAL0_REG_OFST _UINT32_(0x38) /* (ICM_UIHVAL0) User Initial Hash Value n Offset */ 367 #define ICM_UIHVAL1_REG_OFST _UINT32_(0x3C) /* (ICM_UIHVAL1) User Initial Hash Value n Offset */ 368 #define ICM_UIHVAL2_REG_OFST _UINT32_(0x40) /* (ICM_UIHVAL2) User Initial Hash Value n Offset */ 369 #define ICM_UIHVAL3_REG_OFST _UINT32_(0x44) /* (ICM_UIHVAL3) User Initial Hash Value n Offset */ 370 #define ICM_UIHVAL4_REG_OFST _UINT32_(0x48) /* (ICM_UIHVAL4) User Initial Hash Value n Offset */ 371 #define ICM_UIHVAL5_REG_OFST _UINT32_(0x4C) /* (ICM_UIHVAL5) User Initial Hash Value n Offset */ 372 #define ICM_UIHVAL6_REG_OFST _UINT32_(0x50) /* (ICM_UIHVAL6) User Initial Hash Value n Offset */ 373 #define ICM_UIHVAL7_REG_OFST _UINT32_(0x54) /* (ICM_UIHVAL7) User Initial Hash Value n Offset */ 374 375 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 376 /** \brief ICM_DESCRIPTOR register API structure */ 377 typedef struct 378 { /* Integrity Check Monitor */ 379 __IO uint32_t ICM_RADDR; /**< Offset: 0x00 (R/W 32) Region Start Address */ 380 __IO uint32_t ICM_RCFG; /**< Offset: 0x04 (R/W 32) Region Configuration */ 381 __IO uint32_t ICM_RCTRL; /**< Offset: 0x08 (R/W 32) Region Control */ 382 __IO uint32_t ICM_RNEXT; /**< Offset: 0x0C (R/W 32) Region Next Address */ 383 } icm_descriptor_registers_t; 384 385 /** \brief ICM register API structure */ 386 typedef struct 387 { /* Integrity Check Monitor */ 388 __IO uint32_t ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration */ 389 __O uint32_t ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control */ 390 __I uint32_t ICM_SR; /**< Offset: 0x08 (R/ 32) Status */ 391 __I uint8_t Reserved1[0x04]; 392 __O uint32_t ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable */ 393 __O uint32_t ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable */ 394 __I uint32_t ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask */ 395 __I uint32_t ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status */ 396 __I uint32_t ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status */ 397 __I uint8_t Reserved2[0x0C]; 398 __IO uint32_t ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */ 399 __IO uint32_t ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address */ 400 __O uint32_t ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value n */ 401 } icm_registers_t; 402 403 404 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 405 /** \brief ICM_DESCRIPTOR memory section attribute */ 406 #define SECTION_ICM_DESCRIPTOR 407 408 #endif /* _PIC32CXSG61_ICM_COMPONENT_H_ */ 409
