1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_WDT_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_WDT_COMPONENT_FIXUP_H_ 9 10 /* -------- WDT_CTRLA : (WDT Offset: 0x00) (R/W 8) Control -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t :1; /*!< bit: 0 Reserved */ 15 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */ 17 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 18 uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */ 19 } bit; /*!< Structure used for bit access */ 20 uint8_t reg; /*!< Type used for register access */ 21 } WDT_CTRLA_Type; 22 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 23 24 /* -------- WDT_CONFIG : (WDT Offset: 0x01) (R/W 8) Configuration -------- */ 25 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 26 typedef union { 27 struct { 28 uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */ 29 uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */ 30 } bit; /*!< Structure used for bit access */ 31 uint8_t reg; /*!< Type used for register access */ 32 } WDT_CONFIG_Type; 33 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 34 35 /* -------- WDT_EWCTRL : (WDT Offset: 0x02) (R/W 8) Early Warning Interrupt Control -------- */ 36 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 37 typedef union { 38 struct { 39 uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */ 40 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 41 } bit; /*!< Structure used for bit access */ 42 uint8_t reg; /*!< Type used for register access */ 43 } WDT_EWCTRL_Type; 44 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 45 46 /* -------- WDT_INTENCLR : (WDT Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 typedef union { 49 struct { 50 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ 51 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 52 } bit; /*!< Structure used for bit access */ 53 uint8_t reg; /*!< Type used for register access */ 54 } WDT_INTENCLR_Type; 55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 /* -------- WDT_INTENSET : (WDT Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 58 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 59 typedef union { 60 struct { 61 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */ 62 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 63 } bit; /*!< Structure used for bit access */ 64 uint8_t reg; /*!< Type used for register access */ 65 } WDT_INTENSET_Type; 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 67 68 /* -------- WDT_INTFLAG : (WDT Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 69 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 70 typedef union { // __I to avoid read-modify-write on write-to-clear register 71 struct { 72 __I uint8_t EW:1; /*!< bit: 0 Early Warning */ 73 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 74 } bit; /*!< Structure used for bit access */ 75 uint8_t reg; /*!< Type used for register access */ 76 } WDT_INTFLAG_Type; 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 /* -------- WDT_SYNCBUSY : (WDT Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ 80 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 81 typedef union { 82 struct { 83 uint32_t :1; /*!< bit: 0 Reserved */ 84 uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ 85 uint32_t WEN:1; /*!< bit: 2 Window Enable Synchronization Busy */ 86 uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Synchronization Busy */ 87 uint32_t CLEAR:1; /*!< bit: 4 Clear Synchronization Busy */ 88 uint32_t :27; /*!< bit: 5..31 Reserved */ 89 } bit; /*!< Structure used for bit access */ 90 uint32_t reg; /*!< Type used for register access */ 91 } WDT_SYNCBUSY_Type; 92 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 /* -------- WDT_CLEAR : (WDT Offset: 0x0C) ( /W 8) Clear -------- */ 95 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 96 typedef union { 97 struct { 98 uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */ 99 } bit; /*!< Structure used for bit access */ 100 uint8_t reg; /*!< Type used for register access */ 101 } WDT_CLEAR_Type; 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 /** \brief WDT hardware registers */ 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 106 typedef struct { 107 __IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */ 108 __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */ 109 __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */ 110 RoReg8 Reserved1[0x1]; 111 __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ 112 __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ 113 __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ 114 RoReg8 Reserved2[0x1]; 115 __I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */ 116 __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */ 117 } Wdt; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 121 122 #endif /* _MICROCHIP_PIC32CXSG_WDT_COMPONENT_FIXUP_H_ */ 123
