1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_PCC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_PCC_COMPONENT_FIXUP_H_ 9 10 /* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */ 15 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 16 uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */ 17 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 18 uint32_t SCALE:1; /*!< bit: 8 Scale data */ 19 uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */ 20 uint32_t HALFS:1; /*!< bit: 10 Half Sampling */ 21 uint32_t FRSTS:1; /*!< bit: 11 First sample */ 22 uint32_t :4; /*!< bit: 12..15 Reserved */ 23 uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */ 24 uint32_t :11; /*!< bit: 19..29 Reserved */ 25 uint32_t CID:2; /*!< bit: 30..31 Clear If Disabled */ 26 } bit; /*!< Structure used for bit access */ 27 uint32_t reg; /*!< Type used for register access */ 28 } PCC_MR_Type; 29 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 30 31 /* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */ 32 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 33 typedef union { 34 struct { 35 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ 36 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Enable */ 37 uint32_t :30; /*!< bit: 2..31 Reserved */ 38 } bit; /*!< Structure used for bit access */ 39 uint32_t reg; /*!< Type used for register access */ 40 } PCC_IER_Type; 41 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 42 /* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */ 47 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Disable */ 48 uint32_t :30; /*!< bit: 2..31 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } PCC_IDR_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 /* -------- PCC_IMR : (PCC Offset: 0x0C) ( R/ 32) Interrupt Mask Register -------- */ 55 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 56 typedef union { 57 struct { 58 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */ 59 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Mask */ 60 uint32_t :30; /*!< bit: 2..31 Reserved */ 61 } bit; /*!< Structure used for bit access */ 62 uint32_t reg; /*!< Type used for register access */ 63 } PCC_IMR_Type; 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 /* -------- PCC_ISR : (PCC Offset: 0x10) ( R/ 32) Interrupt Status Register -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Status */ 71 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Status */ 72 uint32_t :30; /*!< bit: 2..31 Reserved */ 73 } bit; /*!< Structure used for bit access */ 74 uint32_t reg; /*!< Type used for register access */ 75 } PCC_ISR_Type; 76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 77 78 /* -------- PCC_RHR : (PCC Offset: 0x14) ( R/ 32) Reception Holding Register -------- */ 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 80 typedef union { 81 struct { 82 uint32_t RDATA:32; /*!< bit: 0..31 Reception Data */ 83 } bit; /*!< Structure used for bit access */ 84 uint32_t reg; /*!< Type used for register access */ 85 } PCC_RHR_Type; 86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 87 88 /* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */ 89 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 90 typedef union { 91 struct { 92 uint32_t WPEN:1; /*!< bit: 0 Write Protection Enable */ 93 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 94 uint32_t WPKEY:24; /*!< bit: 8..31 Write Protection Key */ 95 } bit; /*!< Structure used for bit access */ 96 uint32_t reg; /*!< Type used for register access */ 97 } PCC_WPMR_Type; 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 99 100 /* -------- PCC_WPSR : (PCC Offset: 0xE4) ( R/ 32) Write Protection Status Register -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint32_t WPVS:1; /*!< bit: 0 Write Protection Violation Source */ 105 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 106 uint32_t WPVSRC:16; /*!< bit: 8..23 Write Protection Violation Status */ 107 uint32_t :8; /*!< bit: 24..31 Reserved */ 108 } bit; /*!< Structure used for bit access */ 109 uint32_t reg; /*!< Type used for register access */ 110 } PCC_WPSR_Type; 111 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 112 113 /** \brief PCC hardware registers */ 114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 115 typedef struct { 116 __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */ 117 __O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */ 118 __O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */ 119 __I PCC_IMR_Type IMR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Mask Register */ 120 __I PCC_ISR_Type ISR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Status Register */ 121 __I PCC_RHR_Type RHR; /**< \brief Offset: 0x14 (R/ 32) Reception Holding Register */ 122 RoReg8 Reserved1[0xC8]; 123 __IO PCC_WPMR_Type WPMR; /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */ 124 __I PCC_WPSR_Type WPSR; /**< \brief Offset: 0xE4 (R/ 32) Write Protection Status Register */ 125 } Pcc; 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 #endif /* _MICROCHIP_PIC32CXSG_PCC_COMPONENT_FIXUP_H_ */ 129
