1 /* 2 * Component description for PCC 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_PCC_COMPONENT_H_ 22 #define _PIC32CXSG41_PCC_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR PCC */ 26 /* ************************************************************************** */ 27 28 /* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */ 29 #define PCC_MR_RESETVALUE _UINT32_(0x00) /* (PCC_MR) Mode Register Reset Value */ 30 31 #define PCC_MR_PCEN_Pos _UINT32_(0) /* (PCC_MR) Parallel Capture Enable Position */ 32 #define PCC_MR_PCEN_Msk (_UINT32_(0x1) << PCC_MR_PCEN_Pos) /* (PCC_MR) Parallel Capture Enable Mask */ 33 #define PCC_MR_PCEN(value) (PCC_MR_PCEN_Msk & (_UINT32_(value) << PCC_MR_PCEN_Pos)) /* Assignment of value for PCEN in the PCC_MR register */ 34 #define PCC_MR_DSIZE_Pos _UINT32_(4) /* (PCC_MR) Data size Position */ 35 #define PCC_MR_DSIZE_Msk (_UINT32_(0x3) << PCC_MR_DSIZE_Pos) /* (PCC_MR) Data size Mask */ 36 #define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & (_UINT32_(value) << PCC_MR_DSIZE_Pos)) /* Assignment of value for DSIZE in the PCC_MR register */ 37 #define PCC_MR_DSIZE_1DATA_Val _UINT32_(0x0) /* (PCC_MR) 1 data is read in the PCC_RHR */ 38 #define PCC_MR_DSIZE_2DATA_Val _UINT32_(0x1) /* (PCC_MR) 2 data is read in the PCC_RHR */ 39 #define PCC_MR_DSIZE_4DATA_Val _UINT32_(0x2) /* (PCC_MR) 4 data are read in the PCC_RHR (only for 8 bits data size, ISIZE = 0) */ 40 #define PCC_MR_DSIZE_1DATA (PCC_MR_DSIZE_1DATA_Val << PCC_MR_DSIZE_Pos) /* (PCC_MR) 1 data is read in the PCC_RHR Position */ 41 #define PCC_MR_DSIZE_2DATA (PCC_MR_DSIZE_2DATA_Val << PCC_MR_DSIZE_Pos) /* (PCC_MR) 2 data is read in the PCC_RHR Position */ 42 #define PCC_MR_DSIZE_4DATA (PCC_MR_DSIZE_4DATA_Val << PCC_MR_DSIZE_Pos) /* (PCC_MR) 4 data are read in the PCC_RHR (only for 8 bits data size, ISIZE = 0) Position */ 43 #define PCC_MR_SCALE_Pos _UINT32_(8) /* (PCC_MR) Scale data Position */ 44 #define PCC_MR_SCALE_Msk (_UINT32_(0x1) << PCC_MR_SCALE_Pos) /* (PCC_MR) Scale data Mask */ 45 #define PCC_MR_SCALE(value) (PCC_MR_SCALE_Msk & (_UINT32_(value) << PCC_MR_SCALE_Pos)) /* Assignment of value for SCALE in the PCC_MR register */ 46 #define PCC_MR_ALWYS_Pos _UINT32_(9) /* (PCC_MR) Always Sampling Position */ 47 #define PCC_MR_ALWYS_Msk (_UINT32_(0x1) << PCC_MR_ALWYS_Pos) /* (PCC_MR) Always Sampling Mask */ 48 #define PCC_MR_ALWYS(value) (PCC_MR_ALWYS_Msk & (_UINT32_(value) << PCC_MR_ALWYS_Pos)) /* Assignment of value for ALWYS in the PCC_MR register */ 49 #define PCC_MR_HALFS_Pos _UINT32_(10) /* (PCC_MR) Half Sampling Position */ 50 #define PCC_MR_HALFS_Msk (_UINT32_(0x1) << PCC_MR_HALFS_Pos) /* (PCC_MR) Half Sampling Mask */ 51 #define PCC_MR_HALFS(value) (PCC_MR_HALFS_Msk & (_UINT32_(value) << PCC_MR_HALFS_Pos)) /* Assignment of value for HALFS in the PCC_MR register */ 52 #define PCC_MR_FRSTS_Pos _UINT32_(11) /* (PCC_MR) First sample Position */ 53 #define PCC_MR_FRSTS_Msk (_UINT32_(0x1) << PCC_MR_FRSTS_Pos) /* (PCC_MR) First sample Mask */ 54 #define PCC_MR_FRSTS(value) (PCC_MR_FRSTS_Msk & (_UINT32_(value) << PCC_MR_FRSTS_Pos)) /* Assignment of value for FRSTS in the PCC_MR register */ 55 #define PCC_MR_ISIZE_Pos _UINT32_(16) /* (PCC_MR) Input Data Size Position */ 56 #define PCC_MR_ISIZE_Msk (_UINT32_(0x7) << PCC_MR_ISIZE_Pos) /* (PCC_MR) Input Data Size Mask */ 57 #define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & (_UINT32_(value) << PCC_MR_ISIZE_Pos)) /* Assignment of value for ISIZE in the PCC_MR register */ 58 #define PCC_MR_ISIZE_8BITS_Val _UINT32_(0x0) /* (PCC_MR) Input data bus size is 8 bits */ 59 #define PCC_MR_ISIZE_10BITS_Val _UINT32_(0x1) /* (PCC_MR) Input data bus size is 10 bits */ 60 #define PCC_MR_ISIZE_12BITS_Val _UINT32_(0x2) /* (PCC_MR) Input data bus size is 12 bits */ 61 #define PCC_MR_ISIZE_14BITS_Val _UINT32_(0x3) /* (PCC_MR) Input data bus size is 14 bits */ 62 #define PCC_MR_ISIZE_8BITS (PCC_MR_ISIZE_8BITS_Val << PCC_MR_ISIZE_Pos) /* (PCC_MR) Input data bus size is 8 bits Position */ 63 #define PCC_MR_ISIZE_10BITS (PCC_MR_ISIZE_10BITS_Val << PCC_MR_ISIZE_Pos) /* (PCC_MR) Input data bus size is 10 bits Position */ 64 #define PCC_MR_ISIZE_12BITS (PCC_MR_ISIZE_12BITS_Val << PCC_MR_ISIZE_Pos) /* (PCC_MR) Input data bus size is 12 bits Position */ 65 #define PCC_MR_ISIZE_14BITS (PCC_MR_ISIZE_14BITS_Val << PCC_MR_ISIZE_Pos) /* (PCC_MR) Input data bus size is 14 bits Position */ 66 #define PCC_MR_CID_Pos _UINT32_(30) /* (PCC_MR) Clear If Disabled Position */ 67 #define PCC_MR_CID_Msk (_UINT32_(0x3) << PCC_MR_CID_Pos) /* (PCC_MR) Clear If Disabled Mask */ 68 #define PCC_MR_CID(value) (PCC_MR_CID_Msk & (_UINT32_(value) << PCC_MR_CID_Pos)) /* Assignment of value for CID in the PCC_MR register */ 69 #define PCC_MR_Msk _UINT32_(0xC0070F31) /* (PCC_MR) Register Mask */ 70 71 72 /* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */ 73 #define PCC_IER_RESETVALUE _UINT32_(0x00) /* (PCC_IER) Interrupt Enable Register Reset Value */ 74 75 #define PCC_IER_DRDY_Pos _UINT32_(0) /* (PCC_IER) Data Ready Interrupt Enable Position */ 76 #define PCC_IER_DRDY_Msk (_UINT32_(0x1) << PCC_IER_DRDY_Pos) /* (PCC_IER) Data Ready Interrupt Enable Mask */ 77 #define PCC_IER_DRDY(value) (PCC_IER_DRDY_Msk & (_UINT32_(value) << PCC_IER_DRDY_Pos)) /* Assignment of value for DRDY in the PCC_IER register */ 78 #define PCC_IER_OVRE_Pos _UINT32_(1) /* (PCC_IER) Overrun Error Interrupt Enable Position */ 79 #define PCC_IER_OVRE_Msk (_UINT32_(0x1) << PCC_IER_OVRE_Pos) /* (PCC_IER) Overrun Error Interrupt Enable Mask */ 80 #define PCC_IER_OVRE(value) (PCC_IER_OVRE_Msk & (_UINT32_(value) << PCC_IER_OVRE_Pos)) /* Assignment of value for OVRE in the PCC_IER register */ 81 #define PCC_IER_Msk _UINT32_(0x00000003) /* (PCC_IER) Register Mask */ 82 83 84 /* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */ 85 #define PCC_IDR_RESETVALUE _UINT32_(0x00) /* (PCC_IDR) Interrupt Disable Register Reset Value */ 86 87 #define PCC_IDR_DRDY_Pos _UINT32_(0) /* (PCC_IDR) Data Ready Interrupt Disable Position */ 88 #define PCC_IDR_DRDY_Msk (_UINT32_(0x1) << PCC_IDR_DRDY_Pos) /* (PCC_IDR) Data Ready Interrupt Disable Mask */ 89 #define PCC_IDR_DRDY(value) (PCC_IDR_DRDY_Msk & (_UINT32_(value) << PCC_IDR_DRDY_Pos)) /* Assignment of value for DRDY in the PCC_IDR register */ 90 #define PCC_IDR_OVRE_Pos _UINT32_(1) /* (PCC_IDR) Overrun Error Interrupt Disable Position */ 91 #define PCC_IDR_OVRE_Msk (_UINT32_(0x1) << PCC_IDR_OVRE_Pos) /* (PCC_IDR) Overrun Error Interrupt Disable Mask */ 92 #define PCC_IDR_OVRE(value) (PCC_IDR_OVRE_Msk & (_UINT32_(value) << PCC_IDR_OVRE_Pos)) /* Assignment of value for OVRE in the PCC_IDR register */ 93 #define PCC_IDR_Msk _UINT32_(0x00000003) /* (PCC_IDR) Register Mask */ 94 95 96 /* -------- PCC_IMR : (PCC Offset: 0x0C) ( R/ 32) Interrupt Mask Register -------- */ 97 #define PCC_IMR_RESETVALUE _UINT32_(0x00) /* (PCC_IMR) Interrupt Mask Register Reset Value */ 98 99 #define PCC_IMR_DRDY_Pos _UINT32_(0) /* (PCC_IMR) Data Ready Interrupt Mask Position */ 100 #define PCC_IMR_DRDY_Msk (_UINT32_(0x1) << PCC_IMR_DRDY_Pos) /* (PCC_IMR) Data Ready Interrupt Mask Mask */ 101 #define PCC_IMR_DRDY(value) (PCC_IMR_DRDY_Msk & (_UINT32_(value) << PCC_IMR_DRDY_Pos)) /* Assignment of value for DRDY in the PCC_IMR register */ 102 #define PCC_IMR_OVRE_Pos _UINT32_(1) /* (PCC_IMR) Overrun Error Interrupt Mask Position */ 103 #define PCC_IMR_OVRE_Msk (_UINT32_(0x1) << PCC_IMR_OVRE_Pos) /* (PCC_IMR) Overrun Error Interrupt Mask Mask */ 104 #define PCC_IMR_OVRE(value) (PCC_IMR_OVRE_Msk & (_UINT32_(value) << PCC_IMR_OVRE_Pos)) /* Assignment of value for OVRE in the PCC_IMR register */ 105 #define PCC_IMR_Msk _UINT32_(0x00000003) /* (PCC_IMR) Register Mask */ 106 107 108 /* -------- PCC_ISR : (PCC Offset: 0x10) ( R/ 32) Interrupt Status Register -------- */ 109 #define PCC_ISR_RESETVALUE _UINT32_(0x00) /* (PCC_ISR) Interrupt Status Register Reset Value */ 110 111 #define PCC_ISR_DRDY_Pos _UINT32_(0) /* (PCC_ISR) Data Ready Interrupt Status Position */ 112 #define PCC_ISR_DRDY_Msk (_UINT32_(0x1) << PCC_ISR_DRDY_Pos) /* (PCC_ISR) Data Ready Interrupt Status Mask */ 113 #define PCC_ISR_DRDY(value) (PCC_ISR_DRDY_Msk & (_UINT32_(value) << PCC_ISR_DRDY_Pos)) /* Assignment of value for DRDY in the PCC_ISR register */ 114 #define PCC_ISR_OVRE_Pos _UINT32_(1) /* (PCC_ISR) Overrun Error Interrupt Status Position */ 115 #define PCC_ISR_OVRE_Msk (_UINT32_(0x1) << PCC_ISR_OVRE_Pos) /* (PCC_ISR) Overrun Error Interrupt Status Mask */ 116 #define PCC_ISR_OVRE(value) (PCC_ISR_OVRE_Msk & (_UINT32_(value) << PCC_ISR_OVRE_Pos)) /* Assignment of value for OVRE in the PCC_ISR register */ 117 #define PCC_ISR_Msk _UINT32_(0x00000003) /* (PCC_ISR) Register Mask */ 118 119 120 /* -------- PCC_RHR : (PCC Offset: 0x14) ( R/ 32) Reception Holding Register -------- */ 121 #define PCC_RHR_RESETVALUE _UINT32_(0x00) /* (PCC_RHR) Reception Holding Register Reset Value */ 122 123 #define PCC_RHR_RDATA_Pos _UINT32_(0) /* (PCC_RHR) Reception Data Position */ 124 #define PCC_RHR_RDATA_Msk (_UINT32_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos) /* (PCC_RHR) Reception Data Mask */ 125 #define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & (_UINT32_(value) << PCC_RHR_RDATA_Pos)) /* Assignment of value for RDATA in the PCC_RHR register */ 126 #define PCC_RHR_Msk _UINT32_(0xFFFFFFFF) /* (PCC_RHR) Register Mask */ 127 128 129 /* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */ 130 #define PCC_WPMR_RESETVALUE _UINT32_(0x00) /* (PCC_WPMR) Write Protection Mode Register Reset Value */ 131 132 #define PCC_WPMR_WPEN_Pos _UINT32_(0) /* (PCC_WPMR) Write Protection Enable Position */ 133 #define PCC_WPMR_WPEN_Msk (_UINT32_(0x1) << PCC_WPMR_WPEN_Pos) /* (PCC_WPMR) Write Protection Enable Mask */ 134 #define PCC_WPMR_WPEN(value) (PCC_WPMR_WPEN_Msk & (_UINT32_(value) << PCC_WPMR_WPEN_Pos)) /* Assignment of value for WPEN in the PCC_WPMR register */ 135 #define PCC_WPMR_WPKEY_Pos _UINT32_(8) /* (PCC_WPMR) Write Protection Key Position */ 136 #define PCC_WPMR_WPKEY_Msk (_UINT32_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos) /* (PCC_WPMR) Write Protection Key Mask */ 137 #define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & (_UINT32_(value) << PCC_WPMR_WPKEY_Pos)) /* Assignment of value for WPKEY in the PCC_WPMR register */ 138 #define PCC_WPMR_WPKEY_PASSWD_Val _UINT32_(0x504343) /* (PCC_WPMR) Write Protection Key */ 139 #define PCC_WPMR_WPKEY_PASSWD (PCC_WPMR_WPKEY_PASSWD_Val << PCC_WPMR_WPKEY_Pos) /* (PCC_WPMR) Write Protection Key Position */ 140 #define PCC_WPMR_Msk _UINT32_(0xFFFFFF01) /* (PCC_WPMR) Register Mask */ 141 142 143 /* -------- PCC_WPSR : (PCC Offset: 0xE4) ( R/ 32) Write Protection Status Register -------- */ 144 #define PCC_WPSR_RESETVALUE _UINT32_(0x00) /* (PCC_WPSR) Write Protection Status Register Reset Value */ 145 146 #define PCC_WPSR_WPVS_Pos _UINT32_(0) /* (PCC_WPSR) Write Protection Violation Source Position */ 147 #define PCC_WPSR_WPVS_Msk (_UINT32_(0x1) << PCC_WPSR_WPVS_Pos) /* (PCC_WPSR) Write Protection Violation Source Mask */ 148 #define PCC_WPSR_WPVS(value) (PCC_WPSR_WPVS_Msk & (_UINT32_(value) << PCC_WPSR_WPVS_Pos)) /* Assignment of value for WPVS in the PCC_WPSR register */ 149 #define PCC_WPSR_WPVSRC_Pos _UINT32_(8) /* (PCC_WPSR) Write Protection Violation Status Position */ 150 #define PCC_WPSR_WPVSRC_Msk (_UINT32_(0xFFFF) << PCC_WPSR_WPVSRC_Pos) /* (PCC_WPSR) Write Protection Violation Status Mask */ 151 #define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & (_UINT32_(value) << PCC_WPSR_WPVSRC_Pos)) /* Assignment of value for WPVSRC in the PCC_WPSR register */ 152 #define PCC_WPSR_Msk _UINT32_(0x00FFFF01) /* (PCC_WPSR) Register Mask */ 153 154 155 /* PCC register offsets definitions */ 156 #define PCC_MR_REG_OFST _UINT32_(0x00) /* (PCC_MR) Mode Register Offset */ 157 #define PCC_IER_REG_OFST _UINT32_(0x04) /* (PCC_IER) Interrupt Enable Register Offset */ 158 #define PCC_IDR_REG_OFST _UINT32_(0x08) /* (PCC_IDR) Interrupt Disable Register Offset */ 159 #define PCC_IMR_REG_OFST _UINT32_(0x0C) /* (PCC_IMR) Interrupt Mask Register Offset */ 160 #define PCC_ISR_REG_OFST _UINT32_(0x10) /* (PCC_ISR) Interrupt Status Register Offset */ 161 #define PCC_RHR_REG_OFST _UINT32_(0x14) /* (PCC_RHR) Reception Holding Register Offset */ 162 #define PCC_WPMR_REG_OFST _UINT32_(0xE0) /* (PCC_WPMR) Write Protection Mode Register Offset */ 163 #define PCC_WPSR_REG_OFST _UINT32_(0xE4) /* (PCC_WPSR) Write Protection Status Register Offset */ 164 165 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 166 /* PCC register API structure */ 167 typedef struct 168 { /* Parallel Capture Controller */ 169 __IO uint32_t PCC_MR; /* Offset: 0x00 (R/W 32) Mode Register */ 170 __O uint32_t PCC_IER; /* Offset: 0x04 ( /W 32) Interrupt Enable Register */ 171 __O uint32_t PCC_IDR; /* Offset: 0x08 ( /W 32) Interrupt Disable Register */ 172 __I uint32_t PCC_IMR; /* Offset: 0x0C (R/ 32) Interrupt Mask Register */ 173 __I uint32_t PCC_ISR; /* Offset: 0x10 (R/ 32) Interrupt Status Register */ 174 __I uint32_t PCC_RHR; /* Offset: 0x14 (R/ 32) Reception Holding Register */ 175 __I uint8_t Reserved1[0xC8]; 176 __IO uint32_t PCC_WPMR; /* Offset: 0xE0 (R/W 32) Write Protection Mode Register */ 177 __I uint32_t PCC_WPSR; /* Offset: 0xE4 (R/ 32) Write Protection Status Register */ 178 } pcc_registers_t; 179 180 181 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 182 #endif /* _PIC32CXSG41_PCC_COMPONENT_H_ */ 183
