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Searched refs:MEC_BIT (Results 1 – 25 of 57) sorted by relevance

123

/hal_microchip-latest/mec5/drivers/
Dmec_kbc_api.h32 MEC_KBC_IBF_IRQ = MEC_BIT(0),
33 MEC_KBC_OBE_IRQ = MEC_BIT(1),
34 MEC_KBC_PCOBF_EN = MEC_BIT(2),
35 MEC_KBC_AUXOBF_EN = MEC_BIT(3),
36 MEC_KBC_PORT92_EN = MEC_BIT(4),
37 MEC_KBC_GATEA20_FWC_EN = MEC_BIT(5),
38 MEC_KBC_RESET = MEC_BIT(7),
39 MEC_KBC_UD0_SET = MEC_BIT(8),
40 MEC_KBC_UD1_SET = MEC_BIT(9),
41 MEC_KBC_UD2_SET = MEC_BIT(10),
[all …]
Dmec_peci_api.h32 MEC_PECI_CFG_ENABLE = MEC_BIT(0),
33 MEC_PECI_CFG_RESET = MEC_BIT(1),
34 MEC_PECI_CFG_DIS_BIT_TIME_CLAMP = MEC_BIT(2),
35 MEC_PECI_CFG_INTR_EN = MEC_BIT(4),
36 MEC_PECI_CFG_CLK_DIV = MEC_BIT(5),
37 MEC_PECI_CFG_OBT = MEC_BIT(6),
38 MEC_PECI_CFG_REQ_TIMER = MEC_BIT(7),
42 MEC_PECI_IEN_BOF = MEC_BIT(0),
43 MEC_PECI_IEN_EOF = MEC_BIT(1),
44 MEC_PECI_IEN_ERR = MEC_BIT(2),
[all …]
Dmec_espi.c25 if (capabilities & MEC_BIT(MEC_ESPI_CFG_PERIPH_CHAN_SUP_POS)) { in set_supported_channels()
26 temp |= MEC_BIT(MEC_ESPI_IO_CAP0_PC_SUPP_Pos); in set_supported_channels()
29 if (capabilities & MEC_BIT(MEC_ESPI_CFG_VW_CHAN_SUP_POS)) { in set_supported_channels()
30 temp |= MEC_BIT(MEC_ESPI_IO_CAP0_VW_SUPP_Pos); in set_supported_channels()
33 if (capabilities & MEC_BIT(MEC_ESPI_CFG_OOB_CHAN_SUP_POS)) { in set_supported_channels()
34 temp |= MEC_BIT(MEC_ESPI_IO_CAP0_OOB_SUPP_Pos); in set_supported_channels()
37 if (capabilities & MEC_BIT(MEC_ESPI_CFG_FLASH_CHAN_SUP_POS)) { in set_supported_channels()
38 temp |= MEC_BIT(MEC_ESPI_IO_CAP0_FC_SUPP_Pos); in set_supported_channels()
92 if (capabilities & MEC_BIT(MEC_ESPI_CFG_ALERT_OD_SUPP_POS)) { in set_supported_alert_io_pin_mode()
93 temp |= MEC_BIT(MEC_ESPI_IO_CAP1_ALERT_OD_SUPP_Pos); in set_supported_alert_io_pin_mode()
[all …]
Dmec_btimer.c110 regs->CTRL = MEC_BIT(MEC_BTMR_CTRL_RESET_Pos); in mec_hal_btimer_init()
117 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos); in mec_hal_btimer_init()
119 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_AUTO_RELOAD_POS)) { in mec_hal_btimer_init()
120 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_RESTART_Pos); in mec_hal_btimer_init()
123 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_COUNT_UP_POS)) { in mec_hal_btimer_init()
124 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_CNT_DIR_Pos); in mec_hal_btimer_init()
127 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_INTR_EN_POS)) { in mec_hal_btimer_init()
128 regs->IEN |= MEC_BIT(MEC_BTMR_IEN_EVENT_Pos); in mec_hal_btimer_init()
131 if (flags & MEC_BIT(MEC5_BTIMER_CFG_FLAG_START_POS)) { in mec_hal_btimer_init()
132 regs->CTRL |= MEC_BIT(MEC_BTMR_CTRL_START_Pos); in mec_hal_btimer_init()
[all …]
Dmec_ecs.c16 MEC_ECS->INTR_CTRL |= MEC_BIT(MEC_ECS_INTR_CTRL_DIRECT_Pos); in mec_hal_ecs_ictrl()
18 MEC_ECS->INTR_CTRL &= (uint32_t)~MEC_BIT(MEC_ECS_INTR_CTRL_DIRECT_Pos); in mec_hal_ecs_ictrl()
24 if (MEC_ECS->INTR_CTRL & MEC_BIT(MEC_ECS_INTR_CTRL_DIRECT_Pos)) { in mec_hal_ecs_is_idirect()
34 MEC_ECS->AERRC &= (uint32_t)~MEC_BIT(MEC_ECS_AERRC_CAP_Pos); in mec_hal_ecs_ahb_error_ctrl()
36 MEC_ECS->AERRC |= MEC_BIT(MEC_ECS_AERRC_CAP_Pos); in mec_hal_ecs_ahb_error_ctrl()
54 if (MEC_ECS->FEAT_LOCK & MEC_BIT(feature)) { in mec_hal_ecs_is_feature_disabled()
59 if (MEC_ECS->MISC_LOCK & MEC_BIT(feature)) { in mec_hal_ecs_is_feature_disabled()
70 MEC_ECS->ETM_CTRL |= MEC_BIT(MEC_ECS_ETM_CTRL_TRACE_EN_Pos); in mec_hal_ecs_etm_pins()
72 MEC_ECS->ETM_CTRL &= (uint32_t)~MEC_BIT(MEC_ECS_ETM_CTRL_TRACE_EN_Pos); in mec_hal_ecs_etm_pins()
82 msk = (uint32_t)~MEC_BIT(MEC_ECS_DBG_CTRL_EN_Pos); in mec_hal_ecs_debug_port()
[all …]
Dmec_qspi_api.h74 MEC_QSPI_STS_XFR_DONE = MEC_BIT(0),
75 MEC_QSPI_STS_DMA_DONE = MEC_BIT(1),
76 MEC_QSPI_STS_TXB_ERR = MEC_BIT(2), /* overflow TX FIFO or DMA buffer */
77 MEC_QSPI_STS_RXB_ERR = MEC_BIT(3), /* underflow RX FIFO or DMA buffer */
78 MEC_QSPI_STS_PROG_ERR = MEC_BIT(4), /* software misconfigured transfer */
79 MEC_QSPI_STS_LDMA_RX_ERR = MEC_BIT(5), /* Local-DMA error on receive */
80 MEC_QSPI_STS_LDMA_TX_ERR = MEC_BIT(6), /* Local-DMA error on transmit */
81 MEC_QSPI_STS_TXB_FULL = MEC_BIT(8), /* TX FIFO full */
82 MEC_QSPI_STS_TXB_EMPTY = MEC_BIT(9), /* TX FIFO empty */
83 MEC_QSPI_STS_TXB_REQ = MEC_BIT(10), /* TX FIFO reached high water mark */
[all …]
Dmec_adc.c26 if (flags & MEC_BIT(MEC_ADC_SINGLE_INTR_POS)) { in adc_intr_flag_to_bitmap()
27 bm |= MEC_BIT(MEC_ADC_SM_GIRQ_POS); in adc_intr_flag_to_bitmap()
29 if (flags & MEC_BIT(MEC_ADC_REPEAT_INTR_POS)) { in adc_intr_flag_to_bitmap()
30 bm |= MEC_BIT(MEC_ADC_RM_GIRQ_POS); in adc_intr_flag_to_bitmap()
41 uint32_t girq_bm = MEC_BIT(MEC_ADC_SM_GIRQ_POS) | MEC_BIT(MEC_ADC_RM_GIRQ_POS); in mec_hal_adc_init()
58 if (flags & MEC_BIT(MEC_ADC_CFG_SOFT_RESET_POS)) { in mec_hal_adc_init()
59 regs->CTRL = MEC_BIT(MEC_ADC_CTRL_SRST_Pos); in mec_hal_adc_init()
61 if (!(regs->CTRL & MEC_BIT(MEC_ADC_CTRL_SRST_Pos))) { in mec_hal_adc_init()
68 if (flags & MEC_BIT(MEC_ADC_CFG_PWR_SAVE_DIS_POS)) { in mec_hal_adc_init()
69 regs->CTRL |= MEC_BIT(MEC_ADC_CTRL_PWR_SAVE_Pos); in mec_hal_adc_init()
[all …]
Dmec_kscan_api.h30 MEC_KSCAN_CFG_ENABLE = MEC_BIT(0),
31 MEC_KSCAN_CFG_RESET = MEC_BIT(1),
32 MEC_KSCAN_KSO_PREDRIVE_EN = MEC_BIT(2),
33 MEC_KSCAN_KSO_SELECT_DRV_HI = MEC_BIT(3),
34 MEC_KSCAN_INTR_EN = MEC_BIT(4),
60 MEC_KSCAN_IN0 = MEC_BIT(0),
61 MEC_KSCAN_IN1 = MEC_BIT(1),
62 MEC_KSCAN_IN2 = MEC_BIT(2),
63 MEC_KSCAN_IN3 = MEC_BIT(3),
64 MEC_KSCAN_IN4 = MEC_BIT(4),
[all …]
Dmec_espi_fc.c30 (MEC_BIT(MEC_ESPI_IO_FCSTS_BAD_REQ_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_START_OVRFL_Pos) \
31 | MEC_BIT(MEC_ESPI_IO_FCSTS_FAIL_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_DATA_INCOMPL_Pos) \
32 | MEC_BIT(MEC_ESPI_IO_FCSTS_DATA_OVRUN_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_ABORT_FW_Pos) \
33 | MEC_BIT(MEC_ESPI_IO_FCSTS_EC_BUS_ERR_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_DIS_BY_HOST_Pos))
68 iobase->FCRDY = MEC_BIT(MEC_ESPI_IO_FCRDY_FC_READY_Pos); in mec_hal_espi_fc_ready_set()
73 if (iobase->FCRDY & MEC_BIT(MEC_ESPI_IO_FCRDY_FC_READY_Pos)) { in mec_hal_espi_fc_is_ready()
82 if (iobase->FCCFG & MEC_BIT(MEC_ESPI_IO_FCCFG_BUSY_Pos)) { in mec_hal_espi_fc_is_busy()
98 iobase->FCSTS = MEC_ESPI_FC_ERR_ALL | MEC_BIT(MEC_ESPI_IO_FCSTS_DONE_Pos); in mec_hal_espi_fc_op_start()
100 if (flags & MEC_BIT(MEC_ESPI_FC_XFR_FLAG_START_IEN_POS)) { in mec_hal_espi_fc_op_start()
101 iobase->FCIEN |= MEC_BIT(MEC_ESPI_IO_FCIEN_DONE_Pos); in mec_hal_espi_fc_op_start()
[all …]
Dmec_espi_taf.c74 if (flags & MEC_BIT(MEC_ESPI_TAF_INTR_ECP_DONE_POS)) { in iflags_to_bitmap()
75 bitmap |= MEC_BIT(MEC_ESPI_TAF_ECP_GIRQ_POS); in iflags_to_bitmap()
77 if (flags & MEC_BIT(MEC_ESPI_TAF_INTR_HWMON_ERR_POS)) { in iflags_to_bitmap()
78 bitmap |= MEC_BIT(MEC_ESPI_TAF_HWMON_GIRQ_POS); in iflags_to_bitmap()
85 if (regs->PR_DIRTY & MEC_BIT(pridx)) { in pr_is_dirty()
93 uint32_t girq_bm = MEC_BIT(MEC_ESPI_TAF_ECP_GIRQ_POS) | MEC_BIT(MEC_ESPI_TAF_HWMON_GIRQ_POS); in taf_disable_clear_intr()
134 if (src & MEC_BIT(MEC_ESPI_TAF_ECP_GIRQ_POS)) { in mec_hal_espi_taf_girq_status()
135 bitmap |= MEC_BIT(MEC_ESPI_TAF_INTR_ECP_DONE_POS); in mec_hal_espi_taf_girq_status()
137 if (src & MEC_BIT(MEC_ESPI_TAF_HWMON_GIRQ_POS)) { in mec_hal_espi_taf_girq_status()
138 bitmap |= MEC_BIT(MEC_ESPI_TAF_INTR_HWMON_ERR_POS); in mec_hal_espi_taf_girq_status()
[all …]
Dmec_acpi_ec_api.h30 MEC_ACPI_EC_IBF_IRQ = MEC_BIT(0),
31 MEC_ACPI_EC_OBE_IRQ = MEC_BIT(1),
32 MEC_ACPI_EC_4BYTE_MODE = MEC_BIT(2),
33 MEC_ACPI_EC_BURST_MODE = MEC_BIT(4),
34 MEC_ACPI_EC_RESET = MEC_BIT(7),
35 MEC_ACPI_EC_UD0A_SET = MEC_BIT(8),
36 MEC_ACPI_EC_UD1A_SET = MEC_BIT(9),
37 MEC_ACPI_EC_UD0A_ONE = MEC_BIT(16),
38 MEC_ACPI_EC_UD1A_ONE = MEC_BIT(17),
42 MEC_ACPI_EC_STS_OBF = MEC_BIT(0),
[all …]
Dmec_emi_api.h28 MEC_EMI_RESET = MEC_BIT(0),
32 MEC_EMI_SWI_1 = MEC_BIT(1),
33 MEC_EMI_SWI_2 = MEC_BIT(2),
34 MEC_EMI_SWI_3 = MEC_BIT(3),
35 MEC_EMI_SWI_4 = MEC_BIT(4),
36 MEC_EMI_SWI_5 = MEC_BIT(5),
37 MEC_EMI_SWI_6 = MEC_BIT(6),
38 MEC_EMI_SWI_7 = MEC_BIT(7),
39 MEC_EMI_SWI_8 = MEC_BIT(8),
40 MEC_EMI_SWI_9 = MEC_BIT(9),
[all …]
Dmec_wdt.c56 ctrl |= MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos); in mec_hal_wdt_init()
59 ctrl |= MEC_BIT(MEC_WDT_CTRL_STALL_HTMR_Pos); in mec_hal_wdt_init()
62 ctrl |= MEC_BIT(MEC_WDT_CTRL_STALL_WKTMR_Pos); in mec_hal_wdt_init()
65 ctrl |= MEC_BIT(MEC_WDT_CTRL_STALL_JTAG_Pos); in mec_hal_wdt_init()
68 ctrl |= MEC_BIT(MEC_WDT_CTRL_RST_MODE_INTR_Pos); in mec_hal_wdt_init()
69 regs->IEN |= MEC_BIT(MEC_WDT_IEN_INTREN_Pos); in mec_hal_wdt_init()
80 if (regs->CTRL & MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos)) { in mec_hal_wdt_is_enabled()
89 regs->CTRL |= MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos); in mec_hal_wdt_enable()
94 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_WDT_CTRL_ENABLE_Pos); in mec_hal_wdt_disable()
100 regs->CTRL |= MEC_BIT(MEC_WDT_CTRL_RST_MODE_INTR_Pos); in mec_hal_wdt_intr_ctrl()
[all …]
Dmec_bclink.c55 uint32_t girq_bitmap = MEC_BIT(MEC_BCL_BCLR_GIRQ_POS) | MEC_BIT(MEC_BCL_BERR_GIRQ_POS); in mec_hal_bcl_init()
65 base->STATUS = MEC_BIT(MEC_BCL_STATUS_SRST_Pos) | MEC_BIT(MEC_BCL_STATUS_BCERR_Pos); in mec_hal_bcl_init()
73 base->STATUS &= (uint32_t)~MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_init()
87 regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_soft_reset()
89 regs->STATUS = (uint32_t)~MEC_BIT(MEC_BCL_STATUS_SRST_Pos); in mec_hal_bcl_soft_reset()
121 if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BUSY_Pos)) { in mec_hal_bcl_is_busy()
165 if (regs->STATUS & MEC_BIT(MEC_BCL_STATUS_BCERR_Pos)) { in mec_hal_bcl_is_error()
180 regs->STATUS |= MEC_BIT(MEC_BCL_STATUS_BCERR_Pos); in mec_hal_bcl_clear_error()
181 mec_hal_girq_bm_clr_src(MEC_BCL_GIRQ, MEC_BIT(MEC_BCL_BERR_GIRQ_POS)); in mec_hal_bcl_clear_error()
200 mec_hal_girq_bm_clr_src(MEC_BCL_GIRQ, MEC_BIT(MEC_BCL_BCLR_GIRQ_POS)); in mec_hal_bcl_clear_not_busy()
[all …]
Dmec_dmac.c20 #define MEC_DMA_CHAN_ALL_STATUS (MEC_BIT(MEC_DMA_CHAN_ISTATUS_BERR_Pos) \
21 | MEC_BIT(MEC_DMA_CHAN_ISTATUS_HFCREQ_Pos) \
22 | MEC_BIT(MEC_DMA_CHAN_ISTATUS_DONE_Pos) \
23 | MEC_BIT(MEC_DMA_CHAN_ISTATUS_HFCTERM_Pos))
137 base->MCTRL |= MEC_BIT(MEC_DMAC_MCTRL_MRST_Pos); in mec_hal_dmac_reset()
147 base->MCTRL |= MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos); in mec_hal_dmac_enable()
149 base->MCTRL &= (uint32_t)~MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos); in mec_hal_dmac_enable()
159 if (base->MCTRL & MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos)) { in mec_hal_dmac_is_enabled()
218 if (chan_mask & MEC_BIT(chan)) { in mec_hal_dma_chan_ia_enable_mask()
233 if (chan_mask & MEC_BIT(chan)) { in mec_hal_dma_chan_ia_disable_mask()
[all …]
Dmec_rtimer.c35 if (rtmr_config & MEC_BIT(MEC_RTMR_CFG_EN_POS)) { in mec_hal_rtimer_init()
36 ctrl |= MEC_BIT(MEC_RTMR_CTRL_ENABLE_Pos); in mec_hal_rtimer_init()
39 if (rtmr_config & MEC_BIT(MEC_RTMR_CFG_AUTO_RELOAD_POS)) { in mec_hal_rtimer_init()
40 ctrl |= MEC_BIT(MEC_RTMR_CTRL_AUTO_RELOAD_Pos); in mec_hal_rtimer_init()
43 if (rtmr_config & MEC_BIT(MEC_RTMR_CFG_START_POS)) { in mec_hal_rtimer_init()
44 ctrl |= MEC_BIT(MEC_RTMR_CTRL_START_Pos); in mec_hal_rtimer_init()
47 if (rtmr_config & MEC_BIT(MEC_RTMR_CFG_DBG_HALT_POS)) { in mec_hal_rtimer_init()
48 ctrl |= MEC_BIT(MEC_RTMR_CTRL_EXT_HALT_Pos); in mec_hal_rtimer_init()
51 if (rtmr_config & MEC_BIT(MEC_RTMR_CFG_IEN_POS)) { in mec_hal_rtimer_init()
68 return MEC_BIT(MEC_RTMR_STATUS_TERM_POS); in mec_hal_rtimer_status()
[all …]
Dmec_uart.c55 (MEC_BIT(MEC_UART_LCR_PARITY_Pos) | MEC5_UART_ODD_PARITY_REG_VAL),
56 (MEC_BIT(MEC_UART_LCR_PARITY_Pos) | MEC5_UART_EVEN_PARITY_REG_VAL),
57 (MEC_BIT(MEC_UART_LCR_PARITY_Pos) | MEC5_UART_MARK_PARITY_REG_VAL),
58 (MEC_BIT(MEC_UART_LCR_PARITY_Pos) | MEC5_UART_SPACE_PARITY_REG_VAL),
63 (MEC_BIT(MEC_UART_FCR_EXRF_Pos) | (MEC_UART_FCR_RXF_TLVL_1BYTE << MEC_UART_FCR_RXF_TLVL_Pos)),
64 (MEC_BIT(MEC_UART_FCR_EXRF_Pos) | (MEC_UART_FCR_RXF_TLVL_4BYTES << MEC_UART_FCR_RXF_TLVL_Pos)),
65 (MEC_BIT(MEC_UART_FCR_EXRF_Pos) | (MEC_UART_FCR_RXF_TLVL_8BYTES << MEC_UART_FCR_RXF_TLVL_Pos)),
66 (MEC_BIT(MEC_UART_FCR_EXRF_Pos) | (MEC_UART_FCR_RXF_TLVL_14BYTES << MEC_UART_FCR_RXF_TLVL_Pos)),
86 base->LCR |= MEC_BIT(MEC_UART_LCR_DLAB_Pos); in uart_baud_divider_get()
90 base->LCR &= (uint8_t)~MEC_BIT(MEC_UART_LCR_DLAB_Pos); in uart_baud_divider_get()
[all …]
Dmec_i2c.c169 uint8_t control = MEC_BIT(MEC_I2C_SMB_CTRL_PIN_Pos); /* clear low level HW status */ in i2c_config()
174 base->CONFIG |= MEC_BIT(MEC_I2C_SMB_CONFIG_FEN_Pos); /* enable digital filter */ in i2c_config()
195 control = (MEC_BIT(MEC_I2C_SMB_CTRL_PIN_Pos) | MEC_BIT(MEC_I2C_SMB_CTRL_ESO_Pos) in i2c_config()
196 | MEC_BIT(MEC_I2C_SMB_CTRL_ACK_Pos)); in i2c_config()
200 base->CONFIG |= MEC_BIT(MEC_I2C_SMB_CONFIG_ENAB_Pos); in i2c_config()
252 if (!(MEC_BIT(config->port) & MEC5_I2C_SMB_PORT_MAP)) { in mec_hal_i2c_smb_init()
418 if (base->STATUS & MEC_BIT(MEC_I2C_SMB_STATUS_NBB_Pos)) { in mec_hal_i2c_smb_is_bus_owned()
460 ctrl |= MEC_BIT(MEC_I2C_SMB_CTRL_ACK_Pos); in mec_hal_i2c_cmd_ack_ctrl()
462 ctrl &= (uint8_t)~MEC_BIT(MEC_I2C_SMB_CTRL_ACK_Pos); in mec_hal_i2c_cmd_ack_ctrl()
474 uint8_t ctr = (MEC_BIT(MEC_I2C_SMB_CTRL_PIN_Pos) | MEC_BIT(MEC_I2C_SMB_CTRL_ESO_Pos) in mec_hal_i2c_smb_rearm_target_rx()
[all …]
Dmec_bdp.c56 regs->CONFIG = MEC_BIT(MEC_BDP_CFG_REG_SRESET_POS); in mec_hal_bdp_init()
64 if (cfg_flags & MEC_BIT(MEC5_BDP_CFG_ALIAS_EN_POS)) { in mec_hal_bdp_init()
70 if (cfg_flags & MEC_BIT(MEC5_BDP_CFG_THRH_IEN_POS)) { in mec_hal_bdp_init()
71 regs->IEN |= MEC_BIT(MEC_BDP_IEN_REG_THRH_POS); in mec_hal_bdp_init()
75 if (cfg_flags & MEC_BIT(MEC5_BDP_CFG_ALIAS_EN_POS)) { in mec_hal_bdp_init()
76 if (cfg_flags & MEC_BIT(MEC5_BDP_CFG_ALIAS_ACTV_POS)) { in mec_hal_bdp_init()
77 regs->ACTV80A |= MEC_BIT(MEC_BDP_ACTV_REG_EN_POS); in mec_hal_bdp_init()
81 if (cfg_flags & MEC_BIT(MEC5_BDP_CFG_ACTV_POS)) { in mec_hal_bdp_init()
82 regs->ACTV80 |= MEC_BIT(MEC_BDP_ACTV_REG_EN_POS); in mec_hal_bdp_init()
96 regs->ACTV80 |= MEC_BIT(MEC_BDP_ACTV_REG_EN_POS); in mec_hal_bdp_activate()
[all …]
Dmec_qspi.c32 #define MEC_QSPI_STATUS_ERRORS (MEC_BIT(MEC_QSPI_STATUS_TXBERR_Pos) \
33 | MEC_BIT(MEC_QSPI_STATUS_RXBERR_Pos) \
34 | MEC_BIT(MEC_QSPI_STATUS_PROGERR_Pos) \
35 | MEC_BIT(MEC_QSPI_STATUS_LDRXERR_Pos) \
36 | MEC_BIT(MEC_QSPI_STATUS_LDTXERR_Pos))
136 return (regs->MODE & MEC_BIT(MEC_QSPI_MODE_ACTV_Pos)) ? true : false; in mec_hal_qspi_is_enabled()
256 base->MODE |= MEC_BIT(MEC_QSPI_MODE_SRST_Pos); in qspi_reset()
335 base->ALT1_MODE |= MEC_BIT(MEC_QSPI_ALT1_MODE_CS1_ALTEN_Pos); in qspi_cs1_freq()
360 (base->ALT1_MODE & MEC_BIT(MEC_QSPI_ALT1_MODE_CS1_ALTEN_Pos))) { in qspi_compute_byte_time_ns()
540 base->MODE |= MEC_BIT(MEC_QSPI_MODE_ACTV_Pos); in mec_hal_qspi_init()
[all …]
Dmec_espi_oob.c47 bitmap |= MEC_BIT(MEC5_ESPI_OOB_UP_GIRQ_POS); in msk_to_girq_bitmap()
50 bitmap |= MEC_BIT(MEC5_ESPI_OOB_DN_GIRQ_POS); in msk_to_girq_bitmap()
60 if (bitmap & MEC_BIT(MEC5_ESPI_OOB_UP_GIRQ_POS)) { in bitmap_to_msk()
63 if (bitmap & MEC_BIT(MEC5_ESPI_OOB_DN_GIRQ_POS)) { in bitmap_to_msk()
102 iobase->OOBRDY = MEC_BIT(MEC_ESPI_IO_OOBRDY_OOB_READY_Pos); in mec_hal_espi_oob_ready_set()
107 if (iobase->OOBRDY & MEC_BIT(MEC_ESPI_IO_OOBRDY_OOB_READY_Pos)) { in mec_hal_espi_oob_is_ready()
121 uint32_t en = txsts & MEC_BIT(MEC_ESPI_IO_OOBTXSTS_CHEN_CHG_Pos); /* bit[1] */ in mec_hal_espi_oob_en_status()
123 if (txsts & MEC_BIT(MEC_ESPI_IO_OOBTXSTS_CHEN_STATE_Pos)) { in mec_hal_espi_oob_en_status()
124 en |= MEC_BIT(MEC_ESPI_CHAN_ENABLED_POS); in mec_hal_espi_oob_en_status()
204 iobase->OOBRXC |= MEC_BIT(MEC_ESPI_IO_OOBRXC_RX_AVAIL_Pos); in mec_hal_espi_oob_rx_buffer_avail()
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Dmec_kbc.c32 regs->P92ACT |= MEC_BIT(MEC_PORT92_P92ACT_ENABLE_Pos); in port92h_ctrl()
34 regs->P92ACT &= (uint8_t)~MEC_BIT(MEC_PORT92_P92ACT_ENABLE_Pos); in port92h_ctrl()
81 base->ACTV &= (uint8_t)~MEC_BIT(MEC_KBC_ACTV_ENABLE_Pos); in mec_hal_kbc_init()
91 ctrl |= MEC_BIT(MEC_KBC_KECR_SAEN_Pos); in mec_hal_kbc_init()
95 ctrl |= MEC_BIT(MEC_KBC_KECR_OBFEN_Pos); in mec_hal_kbc_init()
99 ctrl |= MEC_BIT(MEC_KBC_KECR_PCOBFEN_Pos); in mec_hal_kbc_init()
102 ctrl |= MEC_BIT(MEC_KBC_KECR_AUXH_Pos); in mec_hal_kbc_init()
107 ctrl |= MEC_BIT(MEC_KBC_KECR_UD3_Pos); in mec_hal_kbc_init()
113 ctrl |= MEC_BIT(MEC_KBC_KECR_UD4_Pos); in mec_hal_kbc_init()
116 ctrl |= MEC_BIT(MEC_KBC_KECR_UD4_Pos + 1); in mec_hal_kbc_init()
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Dmec_pcr.c35 if (MEC_PCR->PRS & MEC_BIT(MEC_PCR_PRS_RESET_VCC_Pos)) { in mec_hal_pcr_is_host_reset()
43 if (MEC_PCR->PRS & MEC_BIT(MEC_PCR_PRS_VCC_PWRGD_Pos)) { in mec_hal_pcr_is_vcc_pwrgd()
58 if (MEC_PCR->TURBO_CLK & MEC_BIT(MEC_PCR_TURBO_CLK_FAST_CLK_Pos)) { in mec_hal_pcr_is_turbo_clock()
64 if (MEC_ECS->FEAT_LOCK & MEC_BIT(MEC_ECS_FEAT_LOCK_TURBO_FREQ_Pos)) { in mec_hal_pcr_is_turbo_clock()
78 if (MEC_PCR->TURBO_CLK & MEC_BIT(MEC_PCR_TURBO_CLK_FAST_CLK_Pos)) { in mec_hal_pcr_cpu_max_freq()
84 if (MEC_ECS->FEAT_LOCK & MEC_BIT(MEC_ECS_FEAT_LOCK_TURBO_FREQ_Pos)) { in mec_hal_pcr_cpu_max_freq()
180 if (MEC_PCR->OID & MEC_BIT(MEC_PCR_OID_PLL_LOCK_Pos)) { in mec_hal_pcr_is_pll_locked()
201 MEC_PCR->SLP_EN[idx] |= MEC_BIT(bpos); in mec_hal_pcr_set_blk_slp_en()
213 MEC_PCR->SLP_EN[idx] &= ~MEC_BIT(bpos); in mec_hal_pcr_clr_blk_slp_en()
225 if (MEC_PCR->SLP_EN[idx] & MEC_BIT(bpos)) { in mec_hal_pcr_is_blk_slp_en()
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Dmec_espi_pc.c24 if (bitmap & MEC_BIT(MEC_ESPI_PC_INTR_CHEN_CHG_POS)) { in xlat_intr_to_hw()
25 hwbm |= MEC_BIT(MEC_ESPI_IO_PCSTS_PCEN_CHG_Pos); in xlat_intr_to_hw()
28 if (bitmap & MEC_BIT(MEC_ESPI_PC_INTR_BMEN_CHG_POS)) { in xlat_intr_to_hw()
29 hwbm |= MEC_BIT(MEC_ESPI_IO_PCSTS_PCBMEN_CHG_Pos); in xlat_intr_to_hw()
32 if (bitmap & MEC_BIT(MEC_ESPI_PC_INTR_BERR_POS)) { in xlat_intr_to_hw()
33 hwbm |= MEC_BIT(MEC_ESPI_IO_PCSTS_EC_BUS_ERR_Pos); in xlat_intr_to_hw()
43 iobase->PCRDY = MEC_BIT(MEC_ESPI_IO_PCRDY_PC_READY_Pos); in mec_hal_espi_pc_ready_set()
48 if (iobase->PCRDY & MEC_BIT(MEC_ESPI_IO_PCRDY_PC_READY_Pos)) { in mec_hal_espi_pc_is_ready()
83 if (temp & MEC_BIT(MEC_ESPI_IO_PCSTS_EC_BUS_ERR_Pos)) { in mec_hal_espi_pc_status()
84 sts |= MEC_BIT(MEC_ESPI_PC_ISTS_BERR_POS); in mec_hal_espi_pc_status()
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Dmec_tach.c81 ctrl |= MEC_BIT(MEC_TACH_CTRL_FILT_IN_Pos); in mec_hal_tach_init()
88 ctrl |= MEC_BIT(MEC_TACH_CTRL_RDMODE_Pos); in mec_hal_tach_init()
92 ctrl |= MEC_BIT(MEC_TACH_CTRL_ENOOL_Pos); in mec_hal_tach_init()
97 ctrl |= MEC_BIT(MEC_TACH_CTRL_CNTRDY_IEN_Pos); in mec_hal_tach_init()
102 ctrl |= MEC_BIT(MEC_TACH_CTRL_INTOG_IEN_Pos); in mec_hal_tach_init()
107 ctrl |= MEC_BIT(MEC_TACH_CTRL_ENABLE_Pos); in mec_hal_tach_init()
122 regs->CTRL |= MEC_BIT(MEC_TACH_CTRL_ENABLE_Pos); in mec_hal_tach_enable()
124 regs->CTRL &= (uint32_t)~MEC_BIT(MEC_TACH_CTRL_ENABLE_Pos); in mec_hal_tach_enable()
134 return (regs->CTRL & MEC_BIT(MEC_TACH_CTRL_ENABLE_Pos)) ? true : false; in mec_hal_tach_is_enabled()
171 if (intr_events & MEC_BIT(MEC5_TACH_IEN_OOL_POS)) { in mec_hal_tach_intr_enable()
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