1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #include <stddef.h>
7 #include <stdint.h>
8 
9 #include "mec_defs.h"
10 #include "device_mec5.h"
11 #include "mec_ecs_api.h"
12 
mec_hal_ecs_ictrl(uint8_t direct_en)13 void mec_hal_ecs_ictrl(uint8_t direct_en)
14 {
15     if (direct_en) {
16         MEC_ECS->INTR_CTRL |= MEC_BIT(MEC_ECS_INTR_CTRL_DIRECT_Pos);
17     } else {
18         MEC_ECS->INTR_CTRL &= (uint32_t)~MEC_BIT(MEC_ECS_INTR_CTRL_DIRECT_Pos);
19     }
20 }
21 
mec_hal_ecs_is_idirect(void)22 int mec_hal_ecs_is_idirect(void)
23 {
24     if (MEC_ECS->INTR_CTRL & MEC_BIT(MEC_ECS_INTR_CTRL_DIRECT_Pos)) {
25         return 1;
26     }
27 
28     return 0;
29 }
30 
mec_hal_ecs_ahb_error_ctrl(uint8_t ahb_err_enable)31 void mec_hal_ecs_ahb_error_ctrl(uint8_t ahb_err_enable)
32 {
33     if (ahb_err_enable) { /* clear AHB error capture disable bit */
34         MEC_ECS->AERRC &= (uint32_t)~MEC_BIT(MEC_ECS_AERRC_CAP_Pos);
35     } else {
36         MEC_ECS->AERRC |= MEC_BIT(MEC_ECS_AERRC_CAP_Pos);
37     }
38 }
39 
mec_hal_ecs_ahb_error_val(uint8_t clr_after_read)40 uint32_t mec_hal_ecs_ahb_error_val(uint8_t clr_after_read)
41 {
42     uint32_t ahb_error_val = MEC_ECS->AERRA;
43 
44     if (clr_after_read) {
45         MEC_ECS->AERRA = 0u;
46     }
47 
48     return ahb_error_val;
49 }
50 
mec_hal_ecs_is_feature_disabled(uint8_t feature)51 int mec_hal_ecs_is_feature_disabled(uint8_t feature)
52 {
53     if (feature < 32) {
54         if (MEC_ECS->FEAT_LOCK & MEC_BIT(feature)) {
55             return 1;
56         }
57     } else if (feature < 64) {
58         feature -= 32;
59         if (MEC_ECS->MISC_LOCK & MEC_BIT(feature)) {
60             return 1;
61         }
62     }
63 
64     return 0;
65 }
66 
mec_hal_ecs_etm_pins(uint8_t enable)67 void mec_hal_ecs_etm_pins(uint8_t enable)
68 {
69     if (enable) {
70         MEC_ECS->ETM_CTRL |= MEC_BIT(MEC_ECS_ETM_CTRL_TRACE_EN_Pos);
71     } else {
72         MEC_ECS->ETM_CTRL &= (uint32_t)~MEC_BIT(MEC_ECS_ETM_CTRL_TRACE_EN_Pos);
73     }
74 }
75 
mec_hal_ecs_debug_port(enum mec_debug_mode mode)76 void mec_hal_ecs_debug_port(enum mec_debug_mode mode)
77 {
78     uint32_t msk, temp, val;
79 
80     switch (mode) {
81     case MEC_DEBUG_MODE_DISABLE:
82         msk = (uint32_t)~MEC_BIT(MEC_ECS_DBG_CTRL_EN_Pos);
83         val = 0u;
84         break;
85     case MEC_DEBUG_MODE_JTAG:
86         msk = MEC_ECS_DBG_CTRL_CFG_Msk;
87         val = MEC_BIT(MEC_ECS_DBG_CTRL_EN_Pos) | (uint32_t)MEC_ECS_DBG_CTRL_CFG_JTAG;
88         break;
89     case MEC_DEBUG_MODE_SWD:
90         msk = MEC_ECS_DBG_CTRL_CFG_Msk;
91         val = MEC_BIT(MEC_ECS_DBG_CTRL_EN_Pos) | (uint32_t)MEC_ECS_DBG_CTRL_CFG_SWD_ONLY;
92         break;
93     case MEC_DEBUG_MODE_SWD_SWV:
94         msk = MEC_ECS_DBG_CTRL_CFG_Msk;
95         val = MEC_BIT(MEC_ECS_DBG_CTRL_EN_Pos) | (uint32_t)MEC_ECS_DBG_CTRL_CFG_SWD_SWV;
96         break;
97     default:
98         return;
99     }
100 
101     temp = MEC_ECS->DBG_CTRL & ~msk;
102     temp |= val;
103     MEC_ECS->DBG_CTRL = temp;
104 }
105 
106 /* -------- Analog Comparator -------- */
107 
108 /* Configure Analog comparator - enables, deep sleep enables, and comparator 0 config lock.
109  * NOTE 1: Once comparator 0 is locked its configuration bits cannot be changed until RESET_SYS.
110  * NOTE 2: Caller responsible for configuring comparator pins.
111  */
mec_hal_ecs_analog_comparator_config(uint32_t config)112 void mec_hal_ecs_analog_comparator_config(uint32_t config)
113 {
114     uint32_t msk = 0, val = 0;
115 
116     msk = MEC_BIT(MEC_ECS_CMPSC_DSLP0_Pos) | MEC_BIT(MEC_ECS_CMPSC_DSLP1_Pos);
117     if (config & MEC_ACMP_CFG_DS0) {
118         val |= MEC_BIT(MEC_ECS_CMPSC_DSLP0_Pos);
119     }
120 
121     if (config & MEC_ACMP_CFG_DS1) {
122         val |= MEC_BIT(MEC_ECS_CMPSC_DSLP1_Pos);
123     }
124 
125     MEC_ECS->CMPSC = (MEC_ECS->CMPSC & (uint32_t)~msk) | val;
126 
127     msk = (MEC_BIT(MEC_ECS_CMPC_EN0_Pos) | MEC_BIT(MEC_ECS_CMPC_LKCFG0_Pos)
128            | MEC_BIT(MEC_ECS_CMPC_EN1_Pos));
129     val = 0;
130     if (config & MEC_ACMP_CFG_EN0) {
131         val |= MEC_BIT(MEC_ECS_CMPC_EN0_Pos);
132     }
133     if (config & MEC_ACMP_CFG_LOCK0) {
134         val |= MEC_BIT(MEC_ECS_CMPC_LKCFG0_Pos);
135     }
136     if (config & MEC_ACMP_CFG_EN1) {
137         val |= MEC_BIT(MEC_ECS_CMPC_EN1_Pos);
138     }
139 
140     MEC_ECS->CMPC = (MEC_ECS->CMPC & (uint32_t)~msk) | val;
141 }
142 
143 /* -------- Embedded Reset -------- */
144 
mec_hal_ecs_emb_reset_is_enabled(void)145 bool mec_hal_ecs_emb_reset_is_enabled(void)
146 {
147     if (MEC_ECS->EMBRST_EN & MEC_BIT(MEC_ECS_EMBRST_EN_EN_Pos)) {
148         return true;
149     }
150     return false;
151 }
152 
mec_hal_ecs_emb_reset_enable(uint8_t enable)153 void mec_hal_ecs_emb_reset_enable(uint8_t enable)
154 {
155     if (enable) {
156         MEC_ECS->EMBRST_EN |= MEC_BIT(MEC_ECS_EMBRST_EN_EN_Pos);
157     } else {
158         MEC_ECS->EMBRST_EN &= (uint32_t)~MEC_BIT(MEC_ECS_EMBRST_EN_EN_Pos);
159     }
160 }
161 
mec_hal_ecs_emb_reset_timeout_get(void)162 uint8_t mec_hal_ecs_emb_reset_timeout_get(void)
163 {
164     return (uint8_t)((MEC_ECS->EMBRST_TMOUT & MEC_ECS_EMBRST_TMOUT_TM1_Msk)
165                      >> MEC_ECS_EMBRST_TMOUT_TM1_Pos);
166 }
167 
mec_hal_ecs_emb_reset_timeout(uint8_t timeout)168 void mec_hal_ecs_emb_reset_timeout(uint8_t timeout)
169 {
170     MEC_ECS->EMBRST_TMOUT = ((MEC_ECS->EMBRST_TMOUT & (uint32_t)~MEC_ECS_EMBRST_TMOUT_TM1_Msk)
171                              | (((uint32_t)timeout << MEC_ECS_EMBRST_TMOUT_TM1_Msk)
172                                 & MEC_ECS_EMBRST_TMOUT_TM1_Msk));
173 }
174 
mec_hal_ecs_emb_reset_status(void)175 uint32_t mec_hal_ecs_emb_reset_status(void)
176 {
177     return MEC_ECS->EMBRST_STS;
178 }
179 
mec_hal_ecs_emb_reset_status_clear(void)180 void mec_hal_ecs_emb_reset_status_clear(void)
181 {
182     MEC_ECS->EMBRST_STS &= (uint32_t)~MEC_BIT(MEC_ECS_EMBRST_STS_RST_Pos);
183 }
184 
mec_hal_ecs_emb_reset_count(void)185 uint32_t mec_hal_ecs_emb_reset_count(void)
186 {
187     return MEC_ECS->EMBRST_CNT;
188 }
189 
190 /* ---- PECI VTT Vref pin control ---- */
mec_hal_ecs_peci_vtt_ref_pin_ctrl(uint8_t enable)191 void mec_hal_ecs_peci_vtt_ref_pin_ctrl(uint8_t enable)
192 {
193     if (enable) {
194         MEC_ECS->PECI_CTRL |= MEC_BIT(MEC_ECS_PECI_CTRL_PINS_Pos);
195     } else {
196         MEC_ECS->PECI_CTRL &= (uint32_t)~MEC_BIT(MEC_ECS_PECI_CTRL_PINS_Pos);
197     }
198 }
199 
mec_hal_ecs_peci_vtt_ref_pin_is_enabled(void)200 uint8_t mec_hal_ecs_peci_vtt_ref_pin_is_enabled(void)
201 {
202     if (MEC_ECS->PECI_CTRL & MEC_BIT(MEC_ECS_PECI_CTRL_PINS_Pos)) {
203         return 1;
204     }
205     return 0;
206 }
207 
208 /* ---- Power management ----
209  * Debug interface and ETM control registers.
210  */
211 
212 #define MEC_ECS_PM_SAVE_ITEMS_CNT 4
213 static uint8_t ecs_pm_save_buf[MEC_ECS_PM_SAVE_ITEMS_CNT];
214 
mec_hal_ecs_debug_ifc_save_disable(void)215 void mec_hal_ecs_debug_ifc_save_disable(void)
216 {
217     ecs_pm_save_buf[0] = (uint8_t)(MEC_ECS->ETM_CTRL & 0xffu);
218     MEC_ECS->ETM_CTRL = 0;
219 
220     ecs_pm_save_buf[1] = (uint8_t)(MEC_ECS->DBG_CTRL & 0xffu);
221     MEC_ECS->DBG_CTRL = 0;
222 }
223 
mec_hal_ecs_debug_ifc_restore(void)224 void mec_hal_ecs_debug_ifc_restore(void)
225 {
226     MEC_ECS->ETM_CTRL = ecs_pm_save_buf[0];
227     MEC_ECS->DBG_CTRL = ecs_pm_save_buf[1];
228 }
229 
230 
mec_hal_ecs_pm_save_disable(void)231 void mec_hal_ecs_pm_save_disable(void)
232 {
233     ecs_pm_save_buf[0] = (uint8_t)(MEC_ECS->ETM_CTRL & 0xffu);
234     ecs_pm_save_buf[1] = (uint8_t)(MEC_ECS->DBG_CTRL & 0xffu);
235     ecs_pm_save_buf[2] = (uint8_t)(MEC_ECS->PECI_CTRL & 0xffu);
236 
237     MEC_ECS->ETM_CTRL = 0;
238     MEC_ECS->DBG_CTRL = 0;
239     MEC_ECS->PECI_CTRL = 1; /* disable VREF_VTT function */
240     /* TODO comparators
241      * The EC Subystem Analog Comparators each have a deep sleep enable
242      * bit which must be set when the comparator is enabled. Check with DE
243      * if these bits allow the comparators to respect SLP_EN from PCR.
244      * PCR SLP_EN[1] bit[29] is EC register bank (ECS).
245      */
246 }
247 
mec_hal_ecs_pm_restore(void)248 void mec_hal_ecs_pm_restore(void)
249 {
250     MEC_ECS->PECI_CTRL = ecs_pm_save_buf[2];
251     MEC_ECS->ETM_CTRL = ecs_pm_save_buf[0];
252     MEC_ECS->DBG_CTRL = ecs_pm_save_buf[1];
253 }
254 /* end mec_ecs.c */
255