Lines Matching refs:MEC_BIT

30     (MEC_BIT(MEC_ESPI_IO_FCSTS_BAD_REQ_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_START_OVRFL_Pos) \
31 | MEC_BIT(MEC_ESPI_IO_FCSTS_FAIL_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_DATA_INCOMPL_Pos) \
32 | MEC_BIT(MEC_ESPI_IO_FCSTS_DATA_OVRUN_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_ABORT_FW_Pos) \
33 | MEC_BIT(MEC_ESPI_IO_FCSTS_EC_BUS_ERR_Pos) | MEC_BIT(MEC_ESPI_IO_FCSTS_DIS_BY_HOST_Pos))
68 iobase->FCRDY = MEC_BIT(MEC_ESPI_IO_FCRDY_FC_READY_Pos); in mec_hal_espi_fc_ready_set()
73 if (iobase->FCRDY & MEC_BIT(MEC_ESPI_IO_FCRDY_FC_READY_Pos)) { in mec_hal_espi_fc_is_ready()
82 if (iobase->FCCFG & MEC_BIT(MEC_ESPI_IO_FCCFG_BUSY_Pos)) { in mec_hal_espi_fc_is_busy()
98 iobase->FCSTS = MEC_ESPI_FC_ERR_ALL | MEC_BIT(MEC_ESPI_IO_FCSTS_DONE_Pos); in mec_hal_espi_fc_op_start()
100 if (flags & MEC_BIT(MEC_ESPI_FC_XFR_FLAG_START_IEN_POS)) { in mec_hal_espi_fc_op_start()
101 iobase->FCIEN |= MEC_BIT(MEC_ESPI_IO_FCIEN_DONE_Pos); in mec_hal_espi_fc_op_start()
103 iobase->FCIEN &= (uint32_t)~MEC_BIT(MEC_ESPI_IO_FCIEN_DONE_Pos); in mec_hal_espi_fc_op_start()
106 iobase->FCCTL |= MEC_BIT(MEC_ESPI_IO_FCCTL_START_Pos); in mec_hal_espi_fc_op_start()
111 iobase->FCCTL |= MEC_BIT(MEC_ESPI_IO_FCCTL_ABORT_Pos); in mec_hal_espi_fc_op_abort()
122 if (msk & MEC_BIT(MEC_ESPI_FC_INTR_DONE_POS)) { in mec_hal_espi_fc_intr_ctrl()
123 r |= MEC_BIT(MEC_ESPI_IO_FCIEN_DONE_Pos); in mec_hal_espi_fc_intr_ctrl()
125 if (msk & MEC_BIT(MEC_ESPI_FC_INTR_CHEN_CHG_POS)) { in mec_hal_espi_fc_intr_ctrl()
126 r |= MEC_BIT(MEC_ESPI_IO_FCIEN_CHEN_CHG_Pos); in mec_hal_espi_fc_intr_ctrl()
308 iobase->FCIEN &= (uint32_t)~MEC_BIT(MEC_ESPI_IO_FCIEN_DONE_Pos); in mec_hal_espi_fc_xfr_start()
309 iobase->FCSTS = MEC_ESPI_FC_ERR_ALL | MEC_BIT(MEC_ESPI_IO_FCSTS_DONE_Pos); in mec_hal_espi_fc_xfr_start()
313 if (flags & MEC_BIT(MEC_ESPI_FC_XFR_FLAG_START_IEN_POS)) { in mec_hal_espi_fc_xfr_start()
314 iobase->FCIEN |= MEC_BIT(MEC_ESPI_IO_FCIEN_DONE_Pos); in mec_hal_espi_fc_xfr_start()
320 | MEC_BIT(MEC_ESPI_IO_FCCTL_START_Pos)); in mec_hal_espi_fc_xfr_start()