20 #define MEC_DMA_CHAN_ALL_STATUS (MEC_BIT(MEC_DMA_CHAN_ISTATUS_BERR_Pos) \
21                                  | MEC_BIT(MEC_DMA_CHAN_ISTATUS_HFCREQ_Pos) \
22                                  | MEC_BIT(MEC_DMA_CHAN_ISTATUS_DONE_Pos) \
23                                  | MEC_BIT(MEC_DMA_CHAN_ISTATUS_HFCTERM_Pos))
137     base->MCTRL |= MEC_BIT(MEC_DMAC_MCTRL_MRST_Pos);  in mec_hal_dmac_reset()
147         base->MCTRL |= MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos);  in mec_hal_dmac_enable()
149         base->MCTRL &= (uint32_t)~MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos);  in mec_hal_dmac_enable()
159     if (base->MCTRL & MEC_BIT(MEC_DMAC_MCTRL_MACTV_Pos)) {  in mec_hal_dmac_is_enabled()
218         if (chan_mask & MEC_BIT(chan)) {  in mec_hal_dma_chan_ia_enable_mask()
233         if (chan_mask & MEC_BIT(chan)) {  in mec_hal_dma_chan_ia_disable_mask()
284     if (hwsts & MEC_BIT(MEC_DMA_CHAN_ISTATUS_BERR_Pos)) {  in mec_hal_dma_chan_intr_status()
285         logical_sts |= MEC_BIT(MEC_DMA_CHAN_STS_BUS_ERR_POS);  in mec_hal_dma_chan_intr_status()
288     if (hwsts & MEC_BIT(MEC_DMA_CHAN_ISTATUS_HFCREQ_Pos)) {  in mec_hal_dma_chan_intr_status()
289         logical_sts |= MEC_BIT(MEC_DMA_CHAN_STS_HFC_OVF_POS);  in mec_hal_dma_chan_intr_status()
292     if (hwsts & MEC_BIT(MEC_DMA_CHAN_ISTATUS_DONE_Pos)) {  in mec_hal_dma_chan_intr_status()
293         logical_sts |= MEC_BIT(MEC_DMA_CHAN_STS_DONE_POS);  in mec_hal_dma_chan_intr_status()
296     if (hwsts & MEC_BIT(MEC_DMA_CHAN_ISTATUS_HFCTERM_Pos)) {  in mec_hal_dma_chan_intr_status()
297         logical_sts |= MEC_BIT(MEC_DMA_CHAN_STS_HFC_TERM_POS);  in mec_hal_dma_chan_intr_status()
314     MEC_ECIA0->GIRQ[MEC_DMAC_GIRQ_IDX].SOURCE = MEC_BIT(chan);  in mec_hal_dma_chan_intr_status_clr()
329         ien_val = MEC_BIT(MEC_DMA_CHAN_IEN_DONE_Pos) | MEC_BIT(MEC_DMA_CHAN_IEN_BERR_Pos);  in mec_hal_dma_chan_intr_en()
352     if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_DHFC_Pos)) {  in mec_hal_dma_chan_start()
356     ctrl &= (uint32_t)~(MEC_BIT(MEC_DMA_CHAN_CTRL_HFC_RUN_Pos)  in mec_hal_dma_chan_start()
357                         | MEC_BIT(MEC_DMA_CHAN_CTRL_SWFC_RUN_Pos));  in mec_hal_dma_chan_start()
360     dbg_mec_dma[chan].actv = MEC_BIT(MEC_DMA_CHAN_ACTV_EN_Pos);  in mec_hal_dma_chan_start()
364     dbg_mec_dma[chan].ctrl = ctrl | MEC_BIT(start_pos);  in mec_hal_dma_chan_start()
370     regs->CTRL = ctrl | MEC_BIT(start_pos);  in mec_hal_dma_chan_start()
371     regs->ACTV = MEC_BIT(MEC_DMA_CHAN_ACTV_EN_Pos);  in mec_hal_dma_chan_start()
384     if (base->CHAN[chan].CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_BUSY_Pos)) {  in mec_hal_dma_chan_is_busy()
394     uint32_t halt = (MEC_BIT(MEC_DMA_CHAN_CTRL_HFC_RUN_Pos)  in mec_hal_dma_chan_halt()
395                      | MEC_BIT(MEC_DMA_CHAN_CTRL_SWFC_RUN_Pos));  in mec_hal_dma_chan_halt()
421     if (regs->CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_BUSY_Pos)) {  in mec_hal_dma_chan_stop()
422         regs->CTRL |= MEC_BIT(MEC_DMA_CHAN_CTRL_ABORT_Pos);  in mec_hal_dma_chan_stop()
424         while (regs->CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_BUSY_Pos)) {  in mec_hal_dma_chan_stop()
433     regs->CTRL &= (uint32_t)~(MEC_BIT(MEC_DMA_CHAN_CTRL_HFC_RUN_Pos)  in mec_hal_dma_chan_stop()
434                               | MEC_BIT(MEC_DMA_CHAN_CTRL_SWFC_RUN_Pos));  in mec_hal_dma_chan_stop()
472         regs->CTRL |= MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos);  in mec_hal_dma_chan_dir_set()
474         regs->CTRL &= (uint32_t)~MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos);  in mec_hal_dma_chan_dir_set()
489     if (base->CHAN[chan].CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos)) {  in mec_hal_dma_chan_dir_get()
574     if (regs->CTRL & MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos)) {  in mec_hal_dma_chan_reload()
628         ctrl |= MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos);  in mec_hal_dma_chan_cfg()
633             ctrl |= MEC_BIT(MEC_DMA_CHAN_CTRL_INCRM_Pos);  in mec_hal_dma_chan_cfg()
636             ctrl |= MEC_BIT(MEC_DMA_CHAN_CTRL_INCRD_Pos);  in mec_hal_dma_chan_cfg()
643             ctrl |= MEC_BIT(MEC_DMA_CHAN_CTRL_INCRD_Pos);  in mec_hal_dma_chan_cfg()
646             ctrl |= MEC_BIT(MEC_DMA_CHAN_CTRL_INCRM_Pos);  in mec_hal_dma_chan_cfg()
654         ctrl |= MEC_BIT(MEC_DMA_CHAN_CTRL_DHFC_Pos);  in mec_hal_dma_chan_cfg()
658     regs->ACTV |= MEC_BIT(MEC_DMA_CHAN_ACTV_EN_Pos);  in mec_hal_dma_chan_cfg()
677     if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_DHFC_Pos)) {  in mec_hal_dma_chan_cfg_get()
683     if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos)) {  in mec_hal_dma_chan_cfg_get()
685         if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_INCRM_Pos)) {  in mec_hal_dma_chan_cfg_get()
688         if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_INCRD_Pos)) {  in mec_hal_dma_chan_cfg_get()
693         if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_INCRM_Pos)) {  in mec_hal_dma_chan_cfg_get()
696         if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_INCRD_Pos)) {  in mec_hal_dma_chan_cfg_get()
709     if (ctrl & MEC_BIT(MEC_DMA_CHAN_CTRL_MEM2DEV_Pos)) {  in mec_hal_dma_chan_cfg_get()