Lines Matching refs:MEC_BIT
74 MEC_QSPI_STS_XFR_DONE = MEC_BIT(0),
75 MEC_QSPI_STS_DMA_DONE = MEC_BIT(1),
76 MEC_QSPI_STS_TXB_ERR = MEC_BIT(2), /* overflow TX FIFO or DMA buffer */
77 MEC_QSPI_STS_RXB_ERR = MEC_BIT(3), /* underflow RX FIFO or DMA buffer */
78 MEC_QSPI_STS_PROG_ERR = MEC_BIT(4), /* software misconfigured transfer */
79 MEC_QSPI_STS_LDMA_RX_ERR = MEC_BIT(5), /* Local-DMA error on receive */
80 MEC_QSPI_STS_LDMA_TX_ERR = MEC_BIT(6), /* Local-DMA error on transmit */
81 MEC_QSPI_STS_TXB_FULL = MEC_BIT(8), /* TX FIFO full */
82 MEC_QSPI_STS_TXB_EMPTY = MEC_BIT(9), /* TX FIFO empty */
83 MEC_QSPI_STS_TXB_REQ = MEC_BIT(10), /* TX FIFO reached high water mark */
84 MEC_QSPI_STS_TXB_STALL = MEC_BIT(11), /* TX FIFO empty when engine requests more data */
85 MEC_QSPI_STS_RXB_FULL = MEC_BIT(12), /* RX FIFO full */
86 MEC_QSPI_STS_RXB_EMPTY = MEC_BIT(13), /* RX FIFO empty */
87 MEC_QSPI_STS_RXB_REQ = MEC_BIT(14), /* RX FIFO reached high water mark */
88 MEC_QSPI_STS_RXB_STALL = MEC_BIT(15), /* No clocks generated due to full RX FIFO */
89 MEC_QSPI_STS_ACTIVE = MEC_BIT(16), /* QSPI is asserting its chip select */
93 MEC_QSPI_IEN_XFR_DONE = MEC_BIT(0),
94 MEC_QSPI_IEN_DMA_DONE = MEC_BIT(1),
95 MEC_QSPI_IEN_TXB_ERR = MEC_BIT(2),
96 MEC_QSPI_IEN_RXB_ERR = MEC_BIT(3),
97 MEC_QSPI_IEN_PROG_ERR = MEC_BIT(4),
98 MEC_QSPI_IEN_LDMA_RX_ERR = MEC_BIT(5),
99 MEC_QSPI_IEN_LDMA_TX_ERR = MEC_BIT(6),
100 MEC_QSPI_IEN_TXB_FULL = MEC_BIT(8),
101 MEC_QSPI_IEN_TXB_EMPTY = MEC_BIT(9),
102 MEC_QSPI_IEN_TXB_REQ = MEC_BIT(10),
103 MEC_QSPI_IEN_RXB_FULL = MEC_BIT(12),
104 MEC_QSPI_IEN_RXB_EMPTY = MEC_BIT(13),
105 MEC_QSPI_IEN_RXB_REQ = MEC_BIT(14),
120 #define MEC_QSPI_FLAG_TX_OPCODE MEC_BIT(0)
121 #define MEC_QSPI_FLAG_TX_ADDR MEC_BIT(1)
122 #define MEC_QSPI_FLAG_TX_DUMCLK MEC_BIT(2)
123 #define MEC_QSPI_FLAG_TX_MODEB MEC_BIT(3)
235 #define MEC5_QSPI_BUILD_DESCR_TX_DATA MEC_BIT(0)
236 #define MEC5_QSPI_BUILD_DESCR_TX_ZEROS MEC_BIT(1)
237 #define MEC5_QSPI_BUILD_DESCR_TX_ONES MEC_BIT(2)
238 #define MEC5_QSPI_BUILD_DESCR_RX_DATA MEC_BIT(3)
278 #define MEC5_QSPI_DCFG1_FLAG_DIR_TX MEC_BIT(2)
279 #define MEC5_QSPI_DCFG1_FLAG_DIR_RX MEC_BIT(3)