Lines Matching refs:MEC_BIT
32 #define MEC_QSPI_STATUS_ERRORS (MEC_BIT(MEC_QSPI_STATUS_TXBERR_Pos) \
33 | MEC_BIT(MEC_QSPI_STATUS_RXBERR_Pos) \
34 | MEC_BIT(MEC_QSPI_STATUS_PROGERR_Pos) \
35 | MEC_BIT(MEC_QSPI_STATUS_LDRXERR_Pos) \
36 | MEC_BIT(MEC_QSPI_STATUS_LDTXERR_Pos))
136 return (regs->MODE & MEC_BIT(MEC_QSPI_MODE_ACTV_Pos)) ? true : false; in mec_hal_qspi_is_enabled()
256 base->MODE |= MEC_BIT(MEC_QSPI_MODE_SRST_Pos); in qspi_reset()
335 base->ALT1_MODE |= MEC_BIT(MEC_QSPI_ALT1_MODE_CS1_ALTEN_Pos); in qspi_cs1_freq()
360 (base->ALT1_MODE & MEC_BIT(MEC_QSPI_ALT1_MODE_CS1_ALTEN_Pos))) { in qspi_compute_byte_time_ns()
540 base->MODE |= MEC_BIT(MEC_QSPI_MODE_ACTV_Pos); in mec_hal_qspi_init()
556 if (options & MEC_BIT(MEC_QSPI_OPT_ACTV_EN_POS)) { in mec_hal_qspi_options()
557 msk |= MEC_BIT(MEC_QSPI_MODE_ACTV_Pos); in mec_hal_qspi_options()
559 val |= MEC_BIT(MEC_QSPI_MODE_ACTV_Pos); in mec_hal_qspi_options()
562 if (options & MEC_BIT(MEC_QSPI_OPT_TAF_DMA_EN_POS)) { in mec_hal_qspi_options()
563 msk |= MEC_BIT(MEC_QSPI_MODE_TAFDMA_Pos); in mec_hal_qspi_options()
565 val |= MEC_BIT(MEC_QSPI_MODE_TAFDMA_Pos); in mec_hal_qspi_options()
568 if (options & MEC_BIT(MEC_QSPI_OPT_RX_LDMA_EN_POS)) { in mec_hal_qspi_options()
569 msk |= MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos); in mec_hal_qspi_options()
571 val |= MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos); in mec_hal_qspi_options()
574 if (options & MEC_BIT(MEC_QSPI_OPT_TX_LDMA_EN_POS)) { in mec_hal_qspi_options()
575 msk |= MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos); in mec_hal_qspi_options()
577 val |= MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos); in mec_hal_qspi_options()
598 base->EXE = MEC_BIT(MEC_QSPI_EXE_STOP_Pos); in mec_hal_qspi_force_stop()
606 while (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_ACTIVE_Pos)) { in mec_hal_qspi_force_stop()
630 if (qsts & MEC_BIT(MEC_QSPI_STATUS_DONE_Pos)) { in mec_hal_qspi_done()
662 qien = (MEC_BIT(MEC_QSPI_INTR_CTRL_DONE_Pos) in qspi_intr_ctrl()
663 | MEC_BIT(MEC_QSPI_INTR_CTRL_TXBERR_Pos) in qspi_intr_ctrl()
664 | MEC_BIT(MEC_QSPI_INTR_CTRL_PROGERR_Pos) in qspi_intr_ctrl()
665 | MEC_BIT(MEC_QSPI_INTR_CTRL_LDRXERR_Pos) in qspi_intr_ctrl()
666 | MEC_BIT(MEC_QSPI_INTR_CTRL_LDTXERR_Pos)); in qspi_intr_ctrl()
701 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_TXBE_Pos)) { in mec_hal_qspi_tx_fifo_is_empty()
712 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_TXBF_Pos)) { in mec_hal_qspi_tx_fifo_is_full()
723 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_RXBE_Pos)) { in mec_hal_qspi_rx_fifo_is_empty()
734 if (base->STATUS & MEC_BIT(MEC_QSPI_STATUS_RXBF_Pos)) { in mec_hal_qspi_rx_fifo_is_full()
750 base->EXE = MEC_BIT(MEC_QSPI_EXE_START_Pos); in mec_hal_qspi_start()
769 if (regs->STATUS & MEC_BIT(MEC_QSPI_STATUS_TXBF_Pos)) { in mec_hal_qspi_wr_tx_fifo()
800 if (regs->STATUS & MEC_BIT(MEC_QSPI_STATUS_RXBE_Pos)) { in mec_hal_qspi_rd_rx_fifo()
819 base->MODE &= ~(MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos) | MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos)); in qspi_ldma_init()
839 uint32_t rctrl = MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_EN_Pos); in qspi_ldma_cfg1()
840 uint32_t wctrl = MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_EN_Pos); in qspi_ldma_cfg1()
857 rctrl |= MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_INCRA_Pos); in qspi_ldma_cfg1()
866 base->TX_LDMA_CHAN[0].CTRL = wctrl | MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_INCRA_Pos); in qspi_ldma_cfg1()
922 descr |= MEC_BIT(MEC_QSPI_DESCR_LAST_Pos); in qspi_gen_ts_clocks()
924 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_CLOSE_POS)) { in qspi_gen_ts_clocks()
925 descr |= MEC_BIT(MEC_QSPI_DESCR_CLOSE_Pos); in qspi_gen_ts_clocks()
929 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_IEN_POS)) { in qspi_gen_ts_clocks()
937 base->EXE = MEC_BIT(MEC_QSPI_EXE_START_Pos); in qspi_gen_ts_clocks()
969 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_CLR_FIFOS_POS)) { in mec_hal_qspi_ldma()
970 base->EXE = MEC_BIT(MEC_QSPI_EXE_CLRF_Pos); in mec_hal_qspi_ldma()
977 base->CTRL |= MEC_BIT(MEC_QSPI_CTRL_DESCR_MODE_Pos); in mec_hal_qspi_ldma()
1004 base->LDMA_RXEN |= MEC_BIT(didx); in mec_hal_qspi_ldma()
1006 base->LDMA_TXEN |= MEC_BIT(didx); in mec_hal_qspi_ldma()
1012 descr = base->DESCR[didx - 1u] | MEC_BIT(MEC_QSPI_DESCR_LAST_Pos); in mec_hal_qspi_ldma()
1013 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_CLOSE_POS)) { in mec_hal_qspi_ldma()
1014 descr |= MEC_BIT(MEC_QSPI_DESCR_CLOSE_Pos); in mec_hal_qspi_ldma()
1024 base->MODE |= (MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos) | MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos)); in mec_hal_qspi_ldma()
1026 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_IEN_POS)) { in mec_hal_qspi_ldma()
1033 if (flags & MEC_BIT(MEC_QSPI_XFR_FLAG_START_POS)) { in mec_hal_qspi_ldma()
1034 base->EXE = MEC_BIT(MEC_QSPI_EXE_START_Pos); in mec_hal_qspi_ldma()
1168 ctrl |= MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_INCRA_Pos); in mec_hal_qspi_ldma_cfg1()
1178 ldma_regs->CTRL = ctrl | MEC_BIT(MEC_QSPI_LDMA_CHAN_CTRL_EN_Pos); in mec_hal_qspi_ldma_cfg1()
1212 dbase |= MEC_BIT(MEC_QSPI_DESCR_RXEN_Pos); in mec_hal_qspi_descrs_cfg1()
1283 regs->LDMA_TXEN |= MEC_BIT(didx); in mec_hal_qspi_load_descrs()
1284 mode |= MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos); in mec_hal_qspi_load_descrs()
1286 regs->LDMA_TXEN &= (uint32_t)~MEC_BIT(didx); in mec_hal_qspi_load_descrs()
1290 if (descr & MEC_BIT(MEC_QSPI_DESCR_RXEN_Pos)) { in mec_hal_qspi_load_descrs()
1293 regs->LDMA_RXEN |= MEC_BIT(didx); in mec_hal_qspi_load_descrs()
1294 mode |= MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos); in mec_hal_qspi_load_descrs()
1296 regs->LDMA_RXEN &= (uint32_t)~MEC_BIT(didx); in mec_hal_qspi_load_descrs()
1301 regs->MODE = (regs->MODE & ~(MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos) in mec_hal_qspi_load_descrs()
1302 | MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos))) | mode; in mec_hal_qspi_load_descrs()
1305 if (flags & MEC_BIT(MEC5_QSPI_LD_FLAGS_LAST_POS)) { in mec_hal_qspi_load_descrs()
1306 regs->DESCR[didx] |= MEC_BIT(MEC_QSPI_DESCR_LAST_Pos); in mec_hal_qspi_load_descrs()
1309 if (flags & MEC_BIT(MEC5_QSPI_LD_FLAGS_CLOSE_ON_LAST_POS)) { in mec_hal_qspi_load_descrs()
1310 regs->DESCR[didx] |= MEC_BIT(MEC_QSPI_DESCR_CLOSE_Pos); in mec_hal_qspi_load_descrs()
1314 regs->CTRL = MEC_BIT(MEC_QSPI_CTRL_DESCR_MODE_Pos); in mec_hal_qspi_load_descrs()