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Searched refs:INTENSET (Results 1 – 24 of 24) sorted by relevance

/hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/
Dtc_component_fixup_pic32cxsg.h357 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
383 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
407 …__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
Dtrng_component_fixup_pic32cxsg.h86 …__IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
Dramecc_component_fixup_pic32cxsg.h84 …__IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set … member
Dwdt_component_fixup_pic32cxsg.h112 …__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set … member
Dfreqm_component_fixup_pic32cxsg.h120 …__IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
Dpm_component_fixup_pic32cxsg.h120 …__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set… member
Dosc32kctrl_component_fixup_pic32cxsg.h140 …__IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set… member
Daes_component_fixup_pic32cxsg.h161 …__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set… member
Dsupc_component_fixup_pic32cxsg.h182 …__IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set… member
Deic_component_fixup_pic32cxsg.h195 …__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set… member
Ddac_component_fixup_pic32cxsg.h225 …__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set… member
Dqspi_component_fixup_pic32cxsg.h223 …__IO QSPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x18 (R/W 32) Interrupt Enable Set… member
Dmclk_component_fixup_pic32cxsg.h202 …__IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set… member
Drtc_component_fixup_pic32cxsg.h849 …__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE0 Interrupt Enab… member
877 …__IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE1 Interrupt Enab… member
907 …__IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x0A (R/W 16) MODE2 Interrupt Enab… member
Dsercom_component_fixup_pic32cxsg.h1210 …__IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enabl… member
1232 …__IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enabl… member
1254 …__IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable… member
1279 …__IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Ena… member
Dnvmctrl_component_fixup_pic32cxsg.h244 …__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x0E (R/W 16) Interrupt Enable Set… member
Dac_component_fixup_pic32cxsg.h263 …__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set… member
Di2s_component_fixup_pic32cxsg.h272 …__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set… member
Dpdec_component_fixup_pic32cxsg.h306 …__IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set… member
Dadc_component_fixup_pic32cxsg.h352 …__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set… member
Dusb_component_fixup_pic32cxsg.h850 …__IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Inter… member
882 …__IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt… member
Doscctrl_component_fixup_pic32cxsg.h353 …__IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set… member
Dpac_component_fixup_pic32cxsg.h288 …__IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set… member
Dtcc_component_fixup_pic32cxsg.h651 …__IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set… member