1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_TCC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_TCC_COMPONENT_FIXUP_H_ 9 10 /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint32_t :3; /*!< bit: 2.. 4 Reserved */ 17 uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ 18 uint32_t :1; /*!< bit: 7 Reserved */ 19 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 20 uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ 21 uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ 22 uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ 23 uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) */ 24 uint32_t :7; /*!< bit: 16..22 Reserved */ 25 uint32_t DMAOS:1; /*!< bit: 23 DMA One-shot Trigger Mode */ 26 uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ 27 uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ 28 uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ 29 uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ 30 uint32_t CPTEN4:1; /*!< bit: 28 Capture Channel 4 Enable */ 31 uint32_t CPTEN5:1; /*!< bit: 29 Capture Channel 5 Enable */ 32 uint32_t :2; /*!< bit: 30..31 Reserved */ 33 } bit; /*!< Structure used for bit access */ 34 struct { 35 uint32_t :24; /*!< bit: 0..23 Reserved */ 36 uint32_t CPTEN:6; /*!< bit: 24..29 Capture Channel x Enable */ 37 uint32_t :2; /*!< bit: 30..31 Reserved */ 38 } vec; /*!< Structure used for vec access */ 39 uint32_t reg; /*!< Type used for register access */ 40 } TCC_CTRLA_Type; 41 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 42 43 /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ 44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 45 typedef union { 46 struct { 47 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 48 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 49 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 50 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ 51 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ 52 } bit; /*!< Structure used for bit access */ 53 uint8_t reg; /*!< Type used for register access */ 54 } TCC_CTRLBCLR_Type; 55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ 58 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 59 typedef union { 60 struct { 61 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 62 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 63 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 64 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ 65 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ 66 } bit; /*!< Structure used for bit access */ 67 uint8_t reg; /*!< Type used for register access */ 68 } TCC_CTRLBSET_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 typedef union { 74 struct { 75 uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ 76 uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ 77 uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ 78 uint32_t STATUS:1; /*!< bit: 3 Status Busy */ 79 uint32_t COUNT:1; /*!< bit: 4 Count Busy */ 80 uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ 81 uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ 82 uint32_t PER:1; /*!< bit: 7 Period Busy */ 83 uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ 84 uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ 85 uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ 86 uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ 87 uint32_t CC4:1; /*!< bit: 12 Compare Channel 4 Busy */ 88 uint32_t CC5:1; /*!< bit: 13 Compare Channel 5 Busy */ 89 uint32_t :18; /*!< bit: 14..31 Reserved */ 90 } bit; /*!< Structure used for bit access */ 91 struct { 92 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 93 uint32_t CC:6; /*!< bit: 8..13 Compare Channel x Busy */ 94 uint32_t :18; /*!< bit: 14..31 Reserved */ 95 } vec; /*!< Structure used for vec access */ 96 uint32_t reg; /*!< Type used for register access */ 97 } TCC_SYNCBUSY_Type; 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 99 100 /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ 105 uint32_t :1; /*!< bit: 2 Reserved */ 106 uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ 107 uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ 108 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ 109 uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ 110 uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ 111 uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ 112 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ 113 uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */ 114 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ 115 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ 116 uint32_t :4; /*!< bit: 28..31 Reserved */ 117 } bit; /*!< Structure used for bit access */ 118 uint32_t reg; /*!< Type used for register access */ 119 } TCC_FCTRLA_Type; 120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ 123 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 124 typedef union { 125 struct { 126 uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ 127 uint32_t :1; /*!< bit: 2 Reserved */ 128 uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ 129 uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ 130 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ 131 uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ 132 uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ 133 uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ 134 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ 135 uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */ 136 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ 137 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ 138 uint32_t :4; /*!< bit: 28..31 Reserved */ 139 } bit; /*!< Structure used for bit access */ 140 uint32_t reg; /*!< Type used for register access */ 141 } TCC_FCTRLB_Type; 142 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 143 144 /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ 145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 146 typedef union { 147 struct { 148 uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ 149 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 150 uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ 151 uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ 152 uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ 153 uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ 154 uint32_t :4; /*!< bit: 12..15 Reserved */ 155 uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ 156 uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ 157 } bit; /*!< Structure used for bit access */ 158 struct { 159 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 160 uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ 161 uint32_t :20; /*!< bit: 12..31 Reserved */ 162 } vec; /*!< Structure used for vec access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } TCC_WEXCTRL_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ 168 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 169 typedef union { 170 struct { 171 uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ 172 uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ 173 uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ 174 uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ 175 uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ 176 uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ 177 uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ 178 uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ 179 uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ 180 uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ 181 uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ 182 uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ 183 uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ 184 uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ 185 uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ 186 uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ 187 uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ 188 uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ 189 uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ 190 uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ 191 uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ 192 uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ 193 uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ 194 uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ 195 uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ 196 uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ 197 } bit; /*!< Structure used for bit access */ 198 struct { 199 uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ 200 uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ 201 uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ 202 uint32_t :8; /*!< bit: 24..31 Reserved */ 203 } vec; /*!< Structure used for vec access */ 204 uint32_t reg; /*!< Type used for register access */ 205 } TCC_DRVCTRL_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ 209 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 210 typedef union { 211 struct { 212 uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ 213 uint8_t :1; /*!< bit: 1 Reserved */ 214 uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ 215 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 216 } bit; /*!< Structure used for bit access */ 217 uint8_t reg; /*!< Type used for register access */ 218 } TCC_DBGCTRL_Type; 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 220 221 /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 223 typedef union { 224 struct { 225 uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ 226 uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ 227 uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ 228 uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ 229 uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ 230 uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ 231 uint32_t :1; /*!< bit: 11 Reserved */ 232 uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ 233 uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ 234 uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ 235 uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ 236 uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ 237 uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ 238 uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ 239 uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ 240 uint32_t MCEI4:1; /*!< bit: 20 Match or Capture Channel 4 Event Input Enable */ 241 uint32_t MCEI5:1; /*!< bit: 21 Match or Capture Channel 5 Event Input Enable */ 242 uint32_t :2; /*!< bit: 22..23 Reserved */ 243 uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ 244 uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ 245 uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ 246 uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ 247 uint32_t MCEO4:1; /*!< bit: 28 Match or Capture Channel 4 Event Output Enable */ 248 uint32_t MCEO5:1; /*!< bit: 29 Match or Capture Channel 5 Event Output Enable */ 249 uint32_t :2; /*!< bit: 30..31 Reserved */ 250 } bit; /*!< Structure used for bit access */ 251 struct { 252 uint32_t :12; /*!< bit: 0..11 Reserved */ 253 uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ 254 uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ 255 uint32_t MCEI:6; /*!< bit: 16..21 Match or Capture Channel x Event Input Enable */ 256 uint32_t :2; /*!< bit: 22..23 Reserved */ 257 uint32_t MCEO:6; /*!< bit: 24..29 Match or Capture Channel x Event Output Enable */ 258 uint32_t :2; /*!< bit: 30..31 Reserved */ 259 } vec; /*!< Structure used for vec access */ 260 uint32_t reg; /*!< Type used for register access */ 261 } TCC_EVCTRL_Type; 262 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 263 264 /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef union { 267 struct { 268 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 269 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ 270 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ 271 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ 272 uint32_t :6; /*!< bit: 4.. 9 Reserved */ 273 uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ 274 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ 275 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ 276 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ 277 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ 278 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ 279 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ 280 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ 281 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ 282 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ 283 uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */ 284 uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */ 285 uint32_t :10; /*!< bit: 22..31 Reserved */ 286 } bit; /*!< Structure used for bit access */ 287 struct { 288 uint32_t :16; /*!< bit: 0..15 Reserved */ 289 uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */ 290 uint32_t :10; /*!< bit: 22..31 Reserved */ 291 } vec; /*!< Structure used for vec access */ 292 uint32_t reg; /*!< Type used for register access */ 293 } TCC_INTENCLR_Type; 294 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 295 296 /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ 297 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 298 typedef union { 299 struct { 300 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 301 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ 302 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ 303 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ 304 uint32_t :6; /*!< bit: 4.. 9 Reserved */ 305 uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ 306 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ 307 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ 308 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ 309 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ 310 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ 311 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ 312 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ 313 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ 314 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ 315 uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */ 316 uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */ 317 uint32_t :10; /*!< bit: 22..31 Reserved */ 318 } bit; /*!< Structure used for bit access */ 319 struct { 320 uint32_t :16; /*!< bit: 0..15 Reserved */ 321 uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */ 322 uint32_t :10; /*!< bit: 22..31 Reserved */ 323 } vec; /*!< Structure used for vec access */ 324 uint32_t reg; /*!< Type used for register access */ 325 } TCC_INTENSET_Type; 326 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 327 328 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ 329 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 330 typedef union { // __I to avoid read-modify-write on write-to-clear register 331 struct { 332 __I uint32_t OVF:1; /*!< bit: 0 Overflow */ 333 __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ 334 __I uint32_t CNT:1; /*!< bit: 2 Counter */ 335 __I uint32_t ERR:1; /*!< bit: 3 Error */ 336 __I uint32_t :6; /*!< bit: 4.. 9 Reserved */ 337 __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ 338 __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ 339 __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ 340 __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ 341 __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ 342 __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ 343 __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ 344 __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ 345 __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ 346 __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ 347 __I uint32_t MC4:1; /*!< bit: 20 Match or Capture 4 */ 348 __I uint32_t MC5:1; /*!< bit: 21 Match or Capture 5 */ 349 __I uint32_t :10; /*!< bit: 22..31 Reserved */ 350 } bit; /*!< Structure used for bit access */ 351 struct { 352 __I uint32_t :16; /*!< bit: 0..15 Reserved */ 353 __I uint32_t MC:6; /*!< bit: 16..21 Match or Capture x */ 354 __I uint32_t :10; /*!< bit: 22..31 Reserved */ 355 } vec; /*!< Structure used for vec access */ 356 uint32_t reg; /*!< Type used for register access */ 357 } TCC_INTFLAG_Type; 358 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 359 360 /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ 361 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 362 typedef union { 363 struct { 364 uint32_t STOP:1; /*!< bit: 0 Stop */ 365 uint32_t IDX:1; /*!< bit: 1 Ramp */ 366 uint32_t UFS:1; /*!< bit: 2 Non-recoverable Update Fault State */ 367 uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ 368 uint32_t SLAVE:1; /*!< bit: 4 Slave */ 369 uint32_t PATTBUFV:1; /*!< bit: 5 Pattern Buffer Valid */ 370 uint32_t :1; /*!< bit: 6 Reserved */ 371 uint32_t PERBUFV:1; /*!< bit: 7 Period Buffer Valid */ 372 uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ 373 uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ 374 uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ 375 uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ 376 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ 377 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ 378 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ 379 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ 380 uint32_t CCBUFV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ 381 uint32_t CCBUFV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ 382 uint32_t CCBUFV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ 383 uint32_t CCBUFV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ 384 uint32_t CCBUFV4:1; /*!< bit: 20 Compare Channel 4 Buffer Valid */ 385 uint32_t CCBUFV5:1; /*!< bit: 21 Compare Channel 5 Buffer Valid */ 386 uint32_t :2; /*!< bit: 22..23 Reserved */ 387 uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ 388 uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ 389 uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ 390 uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ 391 uint32_t CMP4:1; /*!< bit: 28 Compare Channel 4 Value */ 392 uint32_t CMP5:1; /*!< bit: 29 Compare Channel 5 Value */ 393 uint32_t :2; /*!< bit: 30..31 Reserved */ 394 } bit; /*!< Structure used for bit access */ 395 struct { 396 uint32_t :16; /*!< bit: 0..15 Reserved */ 397 uint32_t CCBUFV:6; /*!< bit: 16..21 Compare Channel x Buffer Valid */ 398 uint32_t :2; /*!< bit: 22..23 Reserved */ 399 uint32_t CMP:6; /*!< bit: 24..29 Compare Channel x Value */ 400 uint32_t :2; /*!< bit: 30..31 Reserved */ 401 } vec; /*!< Structure used for vec access */ 402 uint32_t reg; /*!< Type used for register access */ 403 } TCC_STATUS_Type; 404 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 405 406 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ 407 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 408 typedef union { 409 struct { // DITH4 mode 410 uint32_t :4; /*!< bit: 0.. 3 Reserved */ 411 uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ 412 uint32_t :8; /*!< bit: 24..31 Reserved */ 413 } DITH4; /*!< Structure used for DITH4 */ 414 struct { // DITH5 mode 415 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 416 uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ 417 uint32_t :8; /*!< bit: 24..31 Reserved */ 418 } DITH5; /*!< Structure used for DITH5 */ 419 struct { // DITH6 mode 420 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 421 uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ 422 uint32_t :8; /*!< bit: 24..31 Reserved */ 423 } DITH6; /*!< Structure used for DITH6 */ 424 struct { 425 uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ 426 uint32_t :8; /*!< bit: 24..31 Reserved */ 427 } bit; /*!< Structure used for bit access */ 428 uint32_t reg; /*!< Type used for register access */ 429 } TCC_COUNT_Type; 430 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 431 432 /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ 433 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 434 typedef union { 435 struct { 436 uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ 437 uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ 438 uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ 439 uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ 440 uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ 441 uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ 442 uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ 443 uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ 444 uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ 445 uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ 446 uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ 447 uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ 448 uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ 449 uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ 450 uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ 451 uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ 452 } bit; /*!< Structure used for bit access */ 453 struct { 454 uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ 455 uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ 456 } vec; /*!< Structure used for vec access */ 457 uint16_t reg; /*!< Type used for register access */ 458 } TCC_PATT_Type; 459 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 460 461 /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ 462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 463 typedef union { 464 struct { 465 uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ 466 uint32_t :1; /*!< bit: 3 Reserved */ 467 uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ 468 uint32_t :1; /*!< bit: 6 Reserved */ 469 uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ 470 uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ 471 uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ 472 uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ 473 uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ 474 uint32_t :4; /*!< bit: 12..15 Reserved */ 475 uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ 476 uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ 477 uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ 478 uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ 479 uint32_t POL4:1; /*!< bit: 20 Channel 4 Polarity */ 480 uint32_t POL5:1; /*!< bit: 21 Channel 5 Polarity */ 481 uint32_t :2; /*!< bit: 22..23 Reserved */ 482 uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ 483 uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ 484 uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ 485 uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ 486 uint32_t :4; /*!< bit: 28..31 Reserved */ 487 } bit; /*!< Structure used for bit access */ 488 struct { 489 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 490 uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ 491 uint32_t :4; /*!< bit: 12..15 Reserved */ 492 uint32_t POL:6; /*!< bit: 16..21 Channel x Polarity */ 493 uint32_t :2; /*!< bit: 22..23 Reserved */ 494 uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ 495 uint32_t :4; /*!< bit: 28..31 Reserved */ 496 } vec; /*!< Structure used for vec access */ 497 uint32_t reg; /*!< Type used for register access */ 498 } TCC_WAVE_Type; 499 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 500 501 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ 502 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 503 typedef union { 504 struct { // DITH4 mode 505 uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ 506 uint32_t PER:20; /*!< bit: 4..23 Period Value */ 507 uint32_t :8; /*!< bit: 24..31 Reserved */ 508 } DITH4; /*!< Structure used for DITH4 */ 509 struct { // DITH5 mode 510 uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ 511 uint32_t PER:19; /*!< bit: 5..23 Period Value */ 512 uint32_t :8; /*!< bit: 24..31 Reserved */ 513 } DITH5; /*!< Structure used for DITH5 */ 514 struct { // DITH6 mode 515 uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ 516 uint32_t PER:18; /*!< bit: 6..23 Period Value */ 517 uint32_t :8; /*!< bit: 24..31 Reserved */ 518 } DITH6; /*!< Structure used for DITH6 */ 519 struct { 520 uint32_t PER:24; /*!< bit: 0..23 Period Value */ 521 uint32_t :8; /*!< bit: 24..31 Reserved */ 522 } bit; /*!< Structure used for bit access */ 523 uint32_t reg; /*!< Type used for register access */ 524 } TCC_PER_Type; 525 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 527 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ 528 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 529 typedef union { 530 struct { // DITH4 mode 531 uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ 532 uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ 533 uint32_t :8; /*!< bit: 24..31 Reserved */ 534 } DITH4; /*!< Structure used for DITH4 */ 535 struct { // DITH5 mode 536 uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ 537 uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ 538 uint32_t :8; /*!< bit: 24..31 Reserved */ 539 } DITH5; /*!< Structure used for DITH5 */ 540 struct { // DITH6 mode 541 uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ 542 uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ 543 uint32_t :8; /*!< bit: 24..31 Reserved */ 544 } DITH6; /*!< Structure used for DITH6 */ 545 struct { 546 uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ 547 uint32_t :8; /*!< bit: 24..31 Reserved */ 548 } bit; /*!< Structure used for bit access */ 549 uint32_t reg; /*!< Type used for register access */ 550 } TCC_CC_Type; 551 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 552 553 /* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ 554 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 555 typedef union { 556 struct { 557 uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ 558 uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ 559 uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ 560 uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ 561 uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ 562 uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ 563 uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ 564 uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ 565 uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ 566 uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ 567 uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ 568 uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ 569 uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ 570 uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ 571 uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ 572 uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ 573 } bit; /*!< Structure used for bit access */ 574 struct { 575 uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ 576 uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ 577 } vec; /*!< Structure used for vec access */ 578 uint16_t reg; /*!< Type used for register access */ 579 } TCC_PATTBUF_Type; 580 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 581 582 /* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ 583 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 584 typedef union { 585 struct { // DITH4 mode 586 uint32_t DITHERBUF:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ 587 uint32_t PERBUF:20; /*!< bit: 4..23 Period Buffer Value */ 588 uint32_t :8; /*!< bit: 24..31 Reserved */ 589 } DITH4; /*!< Structure used for DITH4 */ 590 struct { // DITH5 mode 591 uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ 592 uint32_t PERBUF:19; /*!< bit: 5..23 Period Buffer Value */ 593 uint32_t :8; /*!< bit: 24..31 Reserved */ 594 } DITH5; /*!< Structure used for DITH5 */ 595 struct { // DITH6 mode 596 uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ 597 uint32_t PERBUF:18; /*!< bit: 6..23 Period Buffer Value */ 598 uint32_t :8; /*!< bit: 24..31 Reserved */ 599 } DITH6; /*!< Structure used for DITH6 */ 600 struct { 601 uint32_t PERBUF:24; /*!< bit: 0..23 Period Buffer Value */ 602 uint32_t :8; /*!< bit: 24..31 Reserved */ 603 } bit; /*!< Structure used for bit access */ 604 uint32_t reg; /*!< Type used for register access */ 605 } TCC_PERBUF_Type; 606 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 607 608 /* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ 609 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 610 typedef union { 611 struct { // DITH4 mode 612 uint32_t CCBUF:4; /*!< bit: 0.. 3 Channel Compare/Capture Buffer Value */ 613 uint32_t DITHERBUF:20; /*!< bit: 4..23 Dithering Buffer Cycle Number */ 614 uint32_t :8; /*!< bit: 24..31 Reserved */ 615 } DITH4; /*!< Structure used for DITH4 */ 616 struct { // DITH5 mode 617 uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ 618 uint32_t CCBUF:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ 619 uint32_t :8; /*!< bit: 24..31 Reserved */ 620 } DITH5; /*!< Structure used for DITH5 */ 621 struct { // DITH6 mode 622 uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ 623 uint32_t CCBUF:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ 624 uint32_t :8; /*!< bit: 24..31 Reserved */ 625 } DITH6; /*!< Structure used for DITH6 */ 626 struct { 627 uint32_t CCBUF:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ 628 uint32_t :8; /*!< bit: 24..31 Reserved */ 629 } bit; /*!< Structure used for bit access */ 630 uint32_t reg; /*!< Type used for register access */ 631 } TCC_CCBUF_Type; 632 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 633 634 /** \brief TCC hardware registers */ 635 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 636 typedef struct { 637 __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 638 __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 639 __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 640 RoReg8 Reserved1[0x2]; 641 __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ 642 __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ 643 __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ 644 __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ 645 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ 646 RoReg8 Reserved2[0x2]; 647 __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ 648 RoReg8 Reserved3[0x1]; 649 __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ 650 __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ 651 __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ 652 __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ 653 __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ 654 __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ 655 __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ 656 RoReg8 Reserved4[0x2]; 657 __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ 658 __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ 659 __IO TCC_CC_Type CC[6]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ 660 RoReg8 Reserved5[0x8]; 661 __IO TCC_PATTBUF_Type PATTBUF; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ 662 RoReg8 Reserved6[0x6]; 663 __IO TCC_PERBUF_Type PERBUF; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ 664 __IO TCC_CCBUF_Type CCBUF[6]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ 665 } Tcc; 666 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 667 668 669 #endif /* _MICROCHIP_PIC32CXSG_TCC_COMPONENT_FIXUP_H_ */ 670
