1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_I2S_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_I2S_COMPONENT_FIXUP_H_ 9 10 /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ 17 uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ 18 uint8_t TXEN:1; /*!< bit: 4 Tx Serializer Enable */ 19 uint8_t RXEN:1; /*!< bit: 5 Rx Serializer Enable */ 20 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 21 } bit; /*!< Structure used for bit access */ 22 struct { 23 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 24 uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ 25 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 26 } vec; /*!< Structure used for vec access */ 27 uint8_t reg; /*!< Type used for register access */ 28 } I2S_CTRLA_Type; 29 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 30 31 /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */ 32 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 33 typedef union { 34 struct { 35 uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ 36 uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ 37 uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ 38 uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ 39 uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ 40 uint32_t FSINV:1; /*!< bit: 9 Frame Sync Invert */ 41 uint32_t FSOUTINV:1; /*!< bit: 10 Frame Sync Output Invert */ 42 uint32_t SCKSEL:1; /*!< bit: 11 Serial Clock Select */ 43 uint32_t SCKOUTINV:1; /*!< bit: 12 Serial Clock Output Invert */ 44 uint32_t MCKSEL:1; /*!< bit: 13 Master Clock Select */ 45 uint32_t MCKEN:1; /*!< bit: 14 Master Clock Enable */ 46 uint32_t MCKOUTINV:1; /*!< bit: 15 Master Clock Output Invert */ 47 uint32_t MCKDIV:6; /*!< bit: 16..21 Master Clock Division Factor */ 48 uint32_t :2; /*!< bit: 22..23 Reserved */ 49 uint32_t MCKOUTDIV:6; /*!< bit: 24..29 Master Clock Output Division Factor */ 50 uint32_t :2; /*!< bit: 30..31 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint32_t reg; /*!< Type used for register access */ 53 } I2S_CLKCTRL_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 58 typedef union { 59 struct { 60 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ 61 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ 62 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 63 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ 64 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ 65 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 66 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ 67 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ 68 uint16_t :2; /*!< bit: 10..11 Reserved */ 69 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ 70 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ 71 uint16_t :2; /*!< bit: 14..15 Reserved */ 72 } bit; /*!< Structure used for bit access */ 73 struct { 74 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ 75 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 76 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ 77 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 78 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ 79 uint16_t :2; /*!< bit: 10..11 Reserved */ 80 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ 81 uint16_t :2; /*!< bit: 14..15 Reserved */ 82 } vec; /*!< Structure used for vec access */ 83 uint16_t reg; /*!< Type used for register access */ 84 } I2S_INTENCLR_Type; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */ 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 89 typedef union { 90 struct { 91 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ 92 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ 93 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 94 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ 95 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ 96 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 97 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ 98 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ 99 uint16_t :2; /*!< bit: 10..11 Reserved */ 100 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ 101 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ 102 uint16_t :2; /*!< bit: 14..15 Reserved */ 103 } bit; /*!< Structure used for bit access */ 104 struct { 105 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ 106 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 107 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ 108 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 109 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ 110 uint16_t :2; /*!< bit: 10..11 Reserved */ 111 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ 112 uint16_t :2; /*!< bit: 14..15 Reserved */ 113 } vec; /*!< Structure used for vec access */ 114 uint16_t reg; /*!< Type used for register access */ 115 } I2S_INTENSET_Type; 116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 117 118 /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */ 119 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 120 typedef union { // __I to avoid read-modify-write on write-to-clear register 121 struct { 122 __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ 123 __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ 124 __I uint16_t :2; /*!< bit: 2.. 3 Reserved */ 125 __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ 126 __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ 127 __I uint16_t :2; /*!< bit: 6.. 7 Reserved */ 128 __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ 129 __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ 130 __I uint16_t :2; /*!< bit: 10..11 Reserved */ 131 __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ 132 __I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ 133 __I uint16_t :2; /*!< bit: 14..15 Reserved */ 134 } bit; /*!< Structure used for bit access */ 135 struct { 136 __I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ 137 __I uint16_t :2; /*!< bit: 2.. 3 Reserved */ 138 __I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ 139 __I uint16_t :2; /*!< bit: 6.. 7 Reserved */ 140 __I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ 141 __I uint16_t :2; /*!< bit: 10..11 Reserved */ 142 __I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ 143 __I uint16_t :2; /*!< bit: 14..15 Reserved */ 144 } vec; /*!< Structure used for vec access */ 145 uint16_t reg; /*!< Type used for register access */ 146 } I2S_INTFLAG_Type; 147 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 148 149 /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) ( R/ 16) Synchronization Status -------- */ 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 151 typedef union { 152 struct { 153 uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ 154 uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ 155 uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ 156 uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ 157 uint16_t TXEN:1; /*!< bit: 4 Tx Serializer Enable Synchronization Status */ 158 uint16_t RXEN:1; /*!< bit: 5 Rx Serializer Enable Synchronization Status */ 159 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 160 uint16_t TXDATA:1; /*!< bit: 8 Tx Data Synchronization Status */ 161 uint16_t RXDATA:1; /*!< bit: 9 Rx Data Synchronization Status */ 162 uint16_t :6; /*!< bit: 10..15 Reserved */ 163 } bit; /*!< Structure used for bit access */ 164 struct { 165 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 166 uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ 167 uint16_t :12; /*!< bit: 4..15 Reserved */ 168 } vec; /*!< Structure used for vec access */ 169 uint16_t reg; /*!< Type used for register access */ 170 } I2S_SYNCBUSY_Type; 171 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 172 173 /* -------- I2S_TXCTRL : (I2S Offset: 0x20) (R/W 32) Tx Serializer Control -------- */ 174 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 175 typedef union { 176 struct { 177 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 178 uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ 179 uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ 180 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 181 uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ 182 uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ 183 uint32_t :1; /*!< bit: 11 Reserved */ 184 uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ 185 uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ 186 uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ 187 uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ 188 uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ 189 uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ 190 uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ 191 uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ 192 uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ 193 uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ 194 uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ 195 uint32_t MONO:1; /*!< bit: 24 Mono Mode */ 196 uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ 197 uint32_t :6; /*!< bit: 26..31 Reserved */ 198 } bit; /*!< Structure used for bit access */ 199 struct { 200 uint32_t :16; /*!< bit: 0..15 Reserved */ 201 uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ 202 uint32_t :8; /*!< bit: 24..31 Reserved */ 203 } vec; /*!< Structure used for vec access */ 204 uint32_t reg; /*!< Type used for register access */ 205 } I2S_TXCTRL_Type; 206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 /* -------- I2S_RXCTRL : (I2S Offset: 0x24) (R/W 32) Rx Serializer Control -------- */ 209 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 210 typedef union { 211 struct { 212 uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ 213 uint32_t :3; /*!< bit: 2.. 4 Reserved */ 214 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ 215 uint32_t :1; /*!< bit: 6 Reserved */ 216 uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ 217 uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ 218 uint32_t :1; /*!< bit: 11 Reserved */ 219 uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ 220 uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ 221 uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ 222 uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ 223 uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ 224 uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ 225 uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ 226 uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ 227 uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ 228 uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ 229 uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ 230 uint32_t MONO:1; /*!< bit: 24 Mono Mode */ 231 uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ 232 uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ 233 uint32_t :5; /*!< bit: 27..31 Reserved */ 234 } bit; /*!< Structure used for bit access */ 235 struct { 236 uint32_t :16; /*!< bit: 0..15 Reserved */ 237 uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ 238 uint32_t :8; /*!< bit: 24..31 Reserved */ 239 } vec; /*!< Structure used for vec access */ 240 uint32_t reg; /*!< Type used for register access */ 241 } I2S_RXCTRL_Type; 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 /* -------- I2S_TXDATA : (I2S Offset: 0x30) ( /W 32) Tx Data -------- */ 245 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 246 typedef union { 247 struct { 248 uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ 249 } bit; /*!< Structure used for bit access */ 250 uint32_t reg; /*!< Type used for register access */ 251 } I2S_TXDATA_Type; 252 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 253 254 /* -------- I2S_RXDATA : (I2S Offset: 0x34) ( R/ 32) Rx Data -------- */ 255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 256 typedef union { 257 struct { 258 uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ 259 } bit; /*!< Structure used for bit access */ 260 uint32_t reg; /*!< Type used for register access */ 261 } I2S_RXDATA_Type; 262 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 263 264 /** \brief I2S hardware registers */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef struct { 267 __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 268 RoReg8 Reserved1[0x3]; 269 __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ 270 __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ 271 RoReg8 Reserved2[0x2]; 272 __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ 273 RoReg8 Reserved3[0x2]; 274 __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ 275 RoReg8 Reserved4[0x2]; 276 __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ 277 RoReg8 Reserved5[0x6]; 278 __IO I2S_TXCTRL_Type TXCTRL; /**< \brief Offset: 0x20 (R/W 32) Tx Serializer Control */ 279 __IO I2S_RXCTRL_Type RXCTRL; /**< \brief Offset: 0x24 (R/W 32) Rx Serializer Control */ 280 RoReg8 Reserved6[0x8]; 281 __O I2S_TXDATA_Type TXDATA; /**< \brief Offset: 0x30 ( /W 32) Tx Data */ 282 __I I2S_RXDATA_Type RXDATA; /**< \brief Offset: 0x34 (R/ 32) Rx Data */ 283 } I2s; 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 285 286 #endif /* _MICROCHIP_PIC32CXSG_I2S_COMPONENT_FIXUP_H_ */ 287
