1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_PAC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_PAC_COMPONENT_FIXUP_H_ 9 10 /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ 15 uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ 16 uint32_t :8; /*!< bit: 24..31 Reserved */ 17 } bit; /*!< Structure used for bit access */ 18 uint32_t reg; /*!< Type used for register access */ 19 } PAC_WRCTRL_Type; 20 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 21 22 /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ 23 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 24 typedef union { 25 struct { 26 uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ 27 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 28 } bit; /*!< Structure used for bit access */ 29 uint8_t reg; /*!< Type used for register access */ 30 } PAC_EVCTRL_Type; 31 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 32 33 /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ 34 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 typedef union { 36 struct { 37 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ 38 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 39 } bit; /*!< Structure used for bit access */ 40 uint8_t reg; /*!< Type used for register access */ 41 } PAC_INTENCLR_Type; 42 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 43 44 /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ 45 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 46 typedef union { 47 struct { 48 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ 49 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } PAC_INTENSET_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ 56 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 57 typedef union { // __I to avoid read-modify-write on write-to-clear register 58 struct { 59 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */ 60 __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */ 61 __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */ 62 __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */ 63 __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */ 64 __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */ 65 __I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */ 66 __I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */ 67 __I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */ 68 __I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */ 69 __I uint32_t HPB3_:1; /*!< bit: 10 HPB3 */ 70 __I uint32_t PUKCC_:1; /*!< bit: 11 PUKCC */ 71 __I uint32_t SDHC0_:1; /*!< bit: 12 SDHC0 */ 72 __I uint32_t SDHC1_:1; /*!< bit: 13 SDHC1 */ 73 __I uint32_t QSPI_:1; /*!< bit: 14 QSPI */ 74 __I uint32_t BKUPRAM_:1; /*!< bit: 15 BKUPRAM */ 75 __I uint32_t :16; /*!< bit: 16..31 Reserved */ 76 } bit; /*!< Structure used for bit access */ 77 uint32_t reg; /*!< Type used for register access */ 78 } PAC_INTFLAGAHB_Type; 79 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ 82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 83 typedef union { // __I to avoid read-modify-write on write-to-clear register 84 struct { 85 __I uint32_t PAC_:1; /*!< bit: 0 PAC */ 86 __I uint32_t PM_:1; /*!< bit: 1 PM */ 87 __I uint32_t MCLK_:1; /*!< bit: 2 MCLK */ 88 __I uint32_t RSTC_:1; /*!< bit: 3 RSTC */ 89 __I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */ 90 __I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */ 91 __I uint32_t SUPC_:1; /*!< bit: 6 SUPC */ 92 __I uint32_t GCLK_:1; /*!< bit: 7 GCLK */ 93 __I uint32_t WDT_:1; /*!< bit: 8 WDT */ 94 __I uint32_t RTC_:1; /*!< bit: 9 RTC */ 95 __I uint32_t EIC_:1; /*!< bit: 10 EIC */ 96 __I uint32_t FREQM_:1; /*!< bit: 11 FREQM */ 97 __I uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 */ 98 __I uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 */ 99 __I uint32_t TC0_:1; /*!< bit: 14 TC0 */ 100 __I uint32_t TC1_:1; /*!< bit: 15 TC1 */ 101 __I uint32_t :16; /*!< bit: 16..31 Reserved */ 102 } bit; /*!< Structure used for bit access */ 103 uint32_t reg; /*!< Type used for register access */ 104 } PAC_INTFLAGA_Type; 105 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 106 107 /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 109 typedef union { // __I to avoid read-modify-write on write-to-clear register 110 struct { 111 __I uint32_t USB_:1; /*!< bit: 0 USB */ 112 __I uint32_t DSU_:1; /*!< bit: 1 DSU */ 113 __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ 114 __I uint32_t CMCC_:1; /*!< bit: 3 CMCC */ 115 __I uint32_t PORT_:1; /*!< bit: 4 PORT */ 116 __I uint32_t DMAC_:1; /*!< bit: 5 DMAC */ 117 __I uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX */ 118 __I uint32_t EVSYS_:1; /*!< bit: 7 EVSYS */ 119 __I uint32_t :1; /*!< bit: 8 Reserved */ 120 __I uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 */ 121 __I uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 */ 122 __I uint32_t TCC0_:1; /*!< bit: 11 TCC0 */ 123 __I uint32_t TCC1_:1; /*!< bit: 12 TCC1 */ 124 __I uint32_t TC2_:1; /*!< bit: 13 TC2 */ 125 __I uint32_t TC3_:1; /*!< bit: 14 TC3 */ 126 __I uint32_t :1; /*!< bit: 15 Reserved */ 127 __I uint32_t RAMECC_:1; /*!< bit: 16 RAMECC */ 128 __I uint32_t :15; /*!< bit: 17..31 Reserved */ 129 } bit; /*!< Structure used for bit access */ 130 uint32_t reg; /*!< Type used for register access */ 131 } PAC_INTFLAGB_Type; 132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 133 134 /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ 135 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 136 typedef union { // __I to avoid read-modify-write on write-to-clear register 137 struct { 138 __I uint32_t CAN0_:1; /*!< bit: 0 CAN0 */ 139 __I uint32_t CAN1_:1; /*!< bit: 1 CAN1 */ 140 __I uint32_t GMAC_:1; /*!< bit: 2 GMAC */ 141 __I uint32_t TCC2_:1; /*!< bit: 3 TCC2 */ 142 __I uint32_t TCC3_:1; /*!< bit: 4 TCC3 */ 143 __I uint32_t TC4_:1; /*!< bit: 5 TC4 */ 144 __I uint32_t TC5_:1; /*!< bit: 6 TC5 */ 145 __I uint32_t PDEC_:1; /*!< bit: 7 PDEC */ 146 __I uint32_t AC_:1; /*!< bit: 8 AC */ 147 __I uint32_t AES_:1; /*!< bit: 9 AES */ 148 __I uint32_t TRNG_:1; /*!< bit: 10 TRNG */ 149 __I uint32_t ICM_:1; /*!< bit: 11 ICM */ 150 __I uint32_t PUKCC_:1; /*!< bit: 12 PUKCC */ 151 __I uint32_t QSPI_:1; /*!< bit: 13 QSPI */ 152 __I uint32_t CCL_:1; /*!< bit: 14 CCL */ 153 __I uint32_t :17; /*!< bit: 15..31 Reserved */ 154 } bit; /*!< Structure used for bit access */ 155 uint32_t reg; /*!< Type used for register access */ 156 } PAC_INTFLAGC_Type; 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 /* -------- PAC_INTFLAGD : (PAC Offset: 0x20) (R/W 32) Peripheral interrupt flag status - Bridge D -------- */ 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 161 typedef union { // __I to avoid read-modify-write on write-to-clear register 162 struct { 163 __I uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 */ 164 __I uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 */ 165 __I uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 */ 166 __I uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 */ 167 __I uint32_t TCC4_:1; /*!< bit: 4 TCC4 */ 168 __I uint32_t TC6_:1; /*!< bit: 5 TC6 */ 169 __I uint32_t TC7_:1; /*!< bit: 6 TC7 */ 170 __I uint32_t ADC0_:1; /*!< bit: 7 ADC0 */ 171 __I uint32_t ADC1_:1; /*!< bit: 8 ADC1 */ 172 __I uint32_t DAC_:1; /*!< bit: 9 DAC */ 173 __I uint32_t I2S_:1; /*!< bit: 10 I2S */ 174 __I uint32_t PCC_:1; /*!< bit: 11 PCC */ 175 __I uint32_t :20; /*!< bit: 12..31 Reserved */ 176 } bit; /*!< Structure used for bit access */ 177 uint32_t reg; /*!< Type used for register access */ 178 } PAC_INTFLAGD_Type; 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 180 181 /* -------- PAC_STATUSA : (PAC Offset: 0x34) ( R/ 32) Peripheral write protection status - Bridge A -------- */ 182 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 183 typedef union { 184 struct { 185 uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ 186 uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */ 187 uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */ 188 uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */ 189 uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */ 190 uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */ 191 uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */ 192 uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */ 193 uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */ 194 uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */ 195 uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */ 196 uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */ 197 uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Protect Enable */ 198 uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Protect Enable */ 199 uint32_t TC0_:1; /*!< bit: 14 TC0 APB Protect Enable */ 200 uint32_t TC1_:1; /*!< bit: 15 TC1 APB Protect Enable */ 201 uint32_t :16; /*!< bit: 16..31 Reserved */ 202 } bit; /*!< Structure used for bit access */ 203 uint32_t reg; /*!< Type used for register access */ 204 } PAC_STATUSA_Type; 205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 206 207 /* -------- PAC_STATUSB : (PAC Offset: 0x38) ( R/ 32) Peripheral write protection status - Bridge B -------- */ 208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 209 typedef union { 210 struct { 211 uint32_t USB_:1; /*!< bit: 0 USB APB Protect Enable */ 212 uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ 213 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ 214 uint32_t CMCC_:1; /*!< bit: 3 CMCC APB Protect Enable */ 215 uint32_t PORT_:1; /*!< bit: 4 PORT APB Protect Enable */ 216 uint32_t DMAC_:1; /*!< bit: 5 DMAC APB Protect Enable */ 217 uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Protect Enable */ 218 uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Protect Enable */ 219 uint32_t :1; /*!< bit: 8 Reserved */ 220 uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Protect Enable */ 221 uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Protect Enable */ 222 uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Protect Enable */ 223 uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Protect Enable */ 224 uint32_t TC2_:1; /*!< bit: 13 TC2 APB Protect Enable */ 225 uint32_t TC3_:1; /*!< bit: 14 TC3 APB Protect Enable */ 226 uint32_t :1; /*!< bit: 15 Reserved */ 227 uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Protect Enable */ 228 uint32_t :15; /*!< bit: 17..31 Reserved */ 229 } bit; /*!< Structure used for bit access */ 230 uint32_t reg; /*!< Type used for register access */ 231 } PAC_STATUSB_Type; 232 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 233 234 /* -------- PAC_STATUSC : (PAC Offset: 0x3C) ( R/ 32) Peripheral write protection status - Bridge C -------- */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef union { 237 struct { 238 uint32_t CAN0_:1; /*!< bit: 0 CAN0 APB Protect Enable */ 239 uint32_t CAN1_:1; /*!< bit: 1 CAN1 APB Protect Enable */ 240 uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Protect Enable */ 241 uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Protect Enable */ 242 uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Protect Enable */ 243 uint32_t TC4_:1; /*!< bit: 5 TC4 APB Protect Enable */ 244 uint32_t TC5_:1; /*!< bit: 6 TC5 APB Protect Enable */ 245 uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Protect Enable */ 246 uint32_t AC_:1; /*!< bit: 8 AC APB Protect Enable */ 247 uint32_t AES_:1; /*!< bit: 9 AES APB Protect Enable */ 248 uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Protect Enable */ 249 uint32_t ICM_:1; /*!< bit: 11 ICM APB Protect Enable */ 250 uint32_t PUKCC_:1; /*!< bit: 12 PUKCC APB Protect Enable */ 251 uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Protect Enable */ 252 uint32_t CCL_:1; /*!< bit: 14 CCL APB Protect Enable */ 253 uint32_t :17; /*!< bit: 15..31 Reserved */ 254 } bit; /*!< Structure used for bit access */ 255 uint32_t reg; /*!< Type used for register access */ 256 } PAC_STATUSC_Type; 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 258 259 /* -------- PAC_STATUSD : (PAC Offset: 0x40) ( R/ 32) Peripheral write protection status - Bridge D -------- */ 260 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 261 typedef union { 262 struct { 263 uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Protect Enable */ 264 uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Protect Enable */ 265 uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Protect Enable */ 266 uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Protect Enable */ 267 uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Protect Enable */ 268 uint32_t TC6_:1; /*!< bit: 5 TC6 APB Protect Enable */ 269 uint32_t TC7_:1; /*!< bit: 6 TC7 APB Protect Enable */ 270 uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Protect Enable */ 271 uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Protect Enable */ 272 uint32_t DAC_:1; /*!< bit: 9 DAC APB Protect Enable */ 273 uint32_t I2S_:1; /*!< bit: 10 I2S APB Protect Enable */ 274 uint32_t PCC_:1; /*!< bit: 11 PCC APB Protect Enable */ 275 uint32_t :20; /*!< bit: 12..31 Reserved */ 276 } bit; /*!< Structure used for bit access */ 277 uint32_t reg; /*!< Type used for register access */ 278 } PAC_STATUSD_Type; 279 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 280 281 /** \brief PAC hardware registers */ 282 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 283 typedef struct { 284 __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ 285 __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ 286 RoReg8 Reserved1[0x3]; 287 __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ 288 __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ 289 RoReg8 Reserved2[0x6]; 290 __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ 291 __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ 292 __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ 293 __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ 294 __IO PAC_INTFLAGD_Type INTFLAGD; /**< \brief Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D */ 295 RoReg8 Reserved3[0x10]; 296 __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ 297 __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ 298 __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ 299 __I PAC_STATUSD_Type STATUSD; /**< \brief Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D */ 300 } Pac; 301 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 302 303 #endif /* _MICROCHIP_PIC32CXSG_PAC_COMPONENT_FIXUP_H_ */ 304
