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Searched refs:SPI_MEM_USER_REG (Results 1 – 25 of 28) sorted by relevance

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/hal_espressif-latest/components/spi_flash/
Dspi_flash_wrap.c90 REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); in spi_flash_wrap_enable_77()
92 REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); in spi_flash_wrap_enable_77()
113 REG_SET_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); in spi_flash_wrap_clear_77()
115 REG_CLR_BIT(SPI_MEM_USER_REG(1), SPI_MEM_FWRITE_QIO); in spi_flash_wrap_clear_77()
/hal_espressif-latest/components/esp_psram/esp32s2/
Desp_psram_impl_quad.c215 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); in psram_exec_cmd()
224 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); in psram_exec_cmd()
344 … SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in psram_set_spi1_cmd_cs_timing()
346 … SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in psram_set_spi1_cmd_cs_timing()
360 … SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in psram_set_spi0_cache_cs_timing()
362 CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M); in psram_set_spi0_cache_cs_timing()
/hal_espressif-latest/zephyr/esp32c3/src/
Dsoc_flash_init.c47 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
51 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_flash_init.c89 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
102 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
/hal_espressif-latest/components/bootloader_support/bootloader_flash/src/
Dbootloader_flash_config_esp32c3.c42 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
45 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
Dbootloader_flash_config_esp32s2.c45 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
48 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
Dbootloader_flash_config_esp32s3.c47 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
55 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
Dbootloader_flash_config_esp32c6.c39 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
Dbootloader_flash_config_esp32h2.c40 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
Dbootloader_flash_config_esp32c2.c41 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in bootloader_flash_cs_timing_config()
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_flash_init.c86 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
90 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmspi_timing_tuning_ll.h277 SET_PERI_REG_MASK(SPI_MEM_USER_REG(spi_num), SPI_MEM_USR_DUMMY); in mspi_timing_ll_set_quad_flash_dummy()
369 return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_SETUP); in mspi_timing_ll_is_cs_setup_enabled()
396 return REG_GET_BIT(SPI_MEM_USER_REG(spi_num), SPI_MEM_CS_HOLD); in mspi_timing_ll_is_cs_hold_enabled()
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_spiflash.c708 REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MOSI); in esp_rom_opiflash_cache_mode_config()
709 REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MISO | SPI_MEM_USR_ADDR); in esp_rom_opiflash_cache_mode_config()
717 REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY); in esp_rom_opiflash_cache_mode_config()
719 REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY); in esp_rom_opiflash_cache_mode_config()
/hal_espressif-latest/components/esp_psram/esp32s3/
Desp_psram_impl_quad.c161 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num)); in psram_exec_cmd()
170 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr); in psram_exec_cmd()
/hal_espressif-latest/zephyr/esp32c6/src/
Dsoc_flash_init.c43 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
/hal_espressif-latest/components/esp_rom/include/esp32s2/rom/
Dspi_flash.h59 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
/hal_espressif-latest/components/esp_rom/include/esp32c3/rom/
Dspi_flash.h23 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
/hal_espressif-latest/zephyr/esp32c2/src/
Dsoc_flash_init.c45 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M); in flash_cs_timing_config()
/hal_espressif-latest/components/esp_rom/include/esp32c6/rom/
Dspi_flash.h23 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
/hal_espressif-latest/components/esp_rom/include/esp32h2/rom/
Dspi_flash.h23 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
/hal_espressif-latest/components/esp_rom/include/esp32s3/rom/
Dspi_flash.h53 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
/hal_espressif-latest/components/esp_rom/include/esp32c2/rom/
Dspi_flash.h23 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1)
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dspi_mem_reg.h328 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) macro
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dspi_mem_reg.h335 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x018) macro
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dspi_mem_reg.h344 #define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x018) macro

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