1 /*
2 Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
3 */
4
5 /*
6 * SPDX-FileCopyrightText: 2013-2022 Espressif Systems (Shanghai) CO LTD
7 *
8 * SPDX-License-Identifier: Apache-2.0
9 */
10
11
12 #include <zephyr/kernel.h>
13
14 #include "sdkconfig.h"
15 #include "string.h"
16 #include "esp_attr.h"
17 #include "esp_err.h"
18 #include "esp_types.h"
19 #include "esp_bit_defs.h"
20 #include "esp_log.h"
21 #include "../esp_psram_impl.h"
22 #include "esp32s2/rom/spi_flash.h"
23 #include "esp32s2/rom/opi_flash.h"
24 #include "esp32s2/rom/efuse.h"
25 #include "esp_rom_efuse.h"
26 #include "soc/spi_reg.h"
27 #include "soc/io_mux_reg.h"
28 #include "esp_private/esp_gpio_reserve.h"
29
30 static const char* TAG = "quad_psram";
31
32 //Commands for PSRAM chip
33 #define PSRAM_READ 0x03
34 #define PSRAM_FAST_READ 0x0B
35 #define PSRAM_FAST_READ_DUMMY 0x3
36 #define PSRAM_FAST_READ_QUAD 0xEB
37 #define PSRAM_FAST_READ_QUAD_DUMMY 0x5
38 #define PSRAM_WRITE 0x02
39 #define PSRAM_QUAD_WRITE 0x38
40 #define PSRAM_ENTER_QMODE 0x35
41 #define PSRAM_EXIT_QMODE 0xF5
42 #define PSRAM_RESET_EN 0x66
43 #define PSRAM_RESET 0x99
44 #define PSRAM_SET_BURST_LEN 0xC0
45 #define PSRAM_DEVICE_ID 0x9F
46 // ID
47 #define PSRAM_ID_KGD_M 0xff
48 #define PSRAM_ID_KGD_S 8
49 #define PSRAM_ID_KGD 0x5d
50 #define PSRAM_ID_EID_M 0xff
51 #define PSRAM_ID_EID_S 16
52
53 // Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
54 //
55 // BIT7 | BIT6 | BIT5 | SIZE(MBIT)
56 // -------------------------------------
57 // 0 | 0 | 0 | 16
58 // 0 | 0 | 1 | 32
59 // 0 | 1 | 0 | 64
60 #define PSRAM_EID_SIZE_M 0x07
61 #define PSRAM_EID_SIZE_S 5
62
63 #define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
64 #define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
65 #define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
66 #define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
67
68 // For the old version 32Mbit psram, using the spicial driver */
69 #define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20)
70 #define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
71
72 // IO-pins for PSRAM.
73 // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
74 // hardcode the flash pins as well, making this code incompatible with either a setup
75 // that has the flash on non-standard pins or ESP32s with built-in flash.
76 #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
77 #define FLASH_CS_IO SPI_CS0_GPIO_NUM
78 // PSRAM clock and cs IO should be configured based on hardware design.
79 #define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
80 #define PSRAM_CS_IO SPI_CS1_GPIO_NUM
81 #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
82 #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
83 #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
84 #define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
85
86 #define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
87 #define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
88
89 #define PSRAM_IO_MATRIX_DUMMY_20M 0
90 #define PSRAM_IO_MATRIX_DUMMY_40M 0
91 #define PSRAM_IO_MATRIX_DUMMY_80M 0
92 #define _SPI_CACHE_PORT 0
93 #define _SPI_FLASH_PORT 1
94 #define _SPI_80M_CLK_DIV 1
95 #define _SPI_40M_CLK_DIV 2
96 #define _SPI_20M_CLK_DIV 4
97
98 typedef enum {
99 PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */
100 PSRAM_CLK_MODE_A1C, /*!< ONE extra clock cycles after CS is set high level */
101 PSRAM_CLK_MODE_A2C, /*!< Two extra clock cycles after CS is set high level */
102 PSRAM_CLK_MODE_ALON, /*!< clock always on */
103 PSRAM_CLK_MODE_MAX,
104 } psram_clk_mode_t;
105
106
107 typedef enum {
108 PSRAM_EID_SIZE_16MBITS = 0,
109 PSRAM_EID_SIZE_32MBITS = 1,
110 PSRAM_EID_SIZE_64MBITS = 2,
111 } psram_eid_size_t;
112
113 typedef struct {
114 uint8_t flash_clk_io;
115 uint8_t flash_cs_io;
116 uint8_t psram_clk_io;
117 uint8_t psram_cs_io;
118 uint8_t psram_spiq_sd0_io;
119 uint8_t psram_spid_sd1_io;
120 uint8_t psram_spiwp_sd3_io;
121 uint8_t psram_spihd_sd2_io;
122 } psram_io_t;
123
124 #define PSRAM_IO_CONF_DEFAULT() { \
125 .flash_clk_io = FLASH_CLK_IO, \
126 .flash_cs_io = FLASH_CS_IO, \
127 .psram_clk_io = PSRAM_CLK_IO, \
128 .psram_cs_io = PSRAM_CS_IO, \
129 .psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO, \
130 .psram_spid_sd1_io = PSRAM_SPID_SD1_IO, \
131 .psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO, \
132 .psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO, \
133 }
134
135 typedef enum {
136 PSRAM_SPI_1 = 0x1,
137 /* PSRAM_SPI_2, */
138 /* PSRAM_SPI_3, */
139 PSRAM_SPI_MAX ,
140 } psram_spi_num_t;
141
142 typedef enum {
143 PSRAM_CMD_QPI,
144 PSRAM_CMD_SPI,
145 } psram_cmd_mode_t;
146
147 typedef enum {
148 PSRAM_CACHE_S80M = 1,
149 PSRAM_CACHE_S40M,
150 PSRAM_CACHE_S26M,
151 PSRAM_CACHE_S20M,
152 PSRAM_CACHE_MAX,
153 } psram_cache_speed_t;
154
155 #if CONFIG_SPIRAM_SPEED_40M
156 #define PSRAM_SPEED PSRAM_CACHE_S40M
157 #elif CONFIG_SPIRAM_SPEED_80M
158 #define PSRAM_SPEED PSRAM_CACHE_S80M
159 #else
160 #define PSRAM_SPEED PSRAM_CACHE_S20M
161 #endif
162
163 typedef esp_rom_spi_cmd_t psram_cmd_t;
164
165 static uint32_t s_psram_id = 0;
166 static void psram_cache_init(psram_cache_speed_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
167 extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
168
169 static uint8_t s_psram_cs_io = (uint8_t)-1;
170
esp_psram_impl_get_cs_io(void)171 uint8_t esp_psram_impl_get_cs_io(void)
172 {
173 return s_psram_cs_io;
174 }
175
psram_set_op_mode(int spi_num,psram_cmd_mode_t mode)176 static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
177 {
178 if (mode == PSRAM_CMD_QPI) {
179 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
180 SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
181 } else if (mode == PSRAM_CMD_SPI) {
182 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
183 }
184 }
_psram_exec_cmd(int spi_num,uint32_t cmd,int cmd_bit_len,uint32_t addr,int addr_bit_len,int dummy_bits,uint8_t * mosi_data,int mosi_bit_len,uint8_t * miso_data,int miso_bit_len)185 static void _psram_exec_cmd(int spi_num,
186 uint32_t cmd, int cmd_bit_len,
187 uint32_t addr, int addr_bit_len,
188 int dummy_bits,
189 uint8_t* mosi_data, int mosi_bit_len,
190 uint8_t* miso_data, int miso_bit_len)
191 {
192 esp_rom_spi_cmd_t conf;
193 uint32_t _addr = addr;
194 conf.addr = &_addr;
195 conf.addrBitLen = addr_bit_len;
196 conf.cmd = cmd;
197 conf.cmdBitLen = cmd_bit_len;
198 conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723
199 conf.txData = (uint32_t*) mosi_data;
200 conf.txDataBitLen = mosi_bit_len;
201 conf.rxData = (uint32_t*) miso_data;
202 conf.rxDataBitLen = miso_bit_len;
203 esp_rom_spi_cmd_config(spi_num, &conf);
204 }
205
psram_exec_cmd(int spi_num,psram_cmd_mode_t mode,uint32_t cmd,int cmd_bit_len,uint32_t addr,int addr_bit_len,int dummy_bits,uint8_t * mosi_data,int mosi_bit_len,uint8_t * miso_data,int miso_bit_len,uint32_t cs_mask,bool is_write_erase_operation)206 void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
207 uint32_t cmd, int cmd_bit_len,
208 uint32_t addr, int addr_bit_len,
209 int dummy_bits,
210 uint8_t* mosi_data, int mosi_bit_len,
211 uint8_t* miso_data, int miso_bit_len,
212 uint32_t cs_mask,
213 bool is_write_erase_operation)
214 {
215 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
216 uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
217 uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
218 uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
219 psram_set_op_mode(spi_num, mode);
220 _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
221 dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
222 esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
223
224 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
225 WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
226 WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
227 WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
228 }
229
230 //exit QPI mode(set back to SPI mode)
psram_disable_qio_mode(int spi_num)231 static void psram_disable_qio_mode(int spi_num)
232 {
233 psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
234 PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
235 0, 0, /* address and address bit len*/
236 0, /* dummy bit len */
237 NULL, 0, /* tx data and tx bit len*/
238 NULL, 0, /* rx data and rx bit len*/
239 CS_PSRAM_SEL, /* cs bit mask*/
240 false); /* whether is program/erase operation */
241 }
242
243 //switch psram burst length(32 bytes or 1024 bytes)
244 //datasheet says it should be 1024 bytes by default
psram_set_wrap_burst_length(int spi_num,psram_cmd_mode_t mode)245 static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
246 {
247 psram_exec_cmd(spi_num, mode,
248 PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
249 0, 0, /* address and address bit len*/
250 0, /* dummy bit len */
251 NULL, 0, /* tx data and tx bit len*/
252 NULL, 0, /* rx data and rx bit len*/
253 CS_PSRAM_SEL, /* cs bit mask*/
254 false); /* whether is program/erase operation */
255 }
256
257 //send reset command to psram, in spi mode
psram_reset_mode(int spi_num)258 static void psram_reset_mode(int spi_num)
259 {
260 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
261 PSRAM_RESET_EN, 8, /* command and command bit len*/
262 0, 0, /* address and address bit len*/
263 0, /* dummy bit len */
264 NULL, 0, /* tx data and tx bit len*/
265 NULL, 0, /* rx data and rx bit len*/
266 CS_PSRAM_SEL, /* cs bit mask*/
267 false); /* whether is program/erase operation */
268
269 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
270 PSRAM_RESET, 8, /* command and command bit len*/
271 0, 0, /* address and address bit len*/
272 0, /* dummy bit len */
273 NULL, 0, /* tx data and tx bit len*/
274 NULL, 0, /* rx data and rx bit len*/
275 CS_PSRAM_SEL, /* cs bit mask*/
276 false); /* whether is program/erase operation */
277 }
278
psram_enable_wrap(uint32_t wrap_size)279 esp_err_t psram_enable_wrap(uint32_t wrap_size)
280 {
281 static uint32_t current_wrap_size = 0;
282 if (current_wrap_size == wrap_size) {
283 return ESP_OK;
284 }
285 switch (wrap_size) {
286 case 32:
287 case 0:
288 psram_set_wrap_burst_length(PSRAM_SPI_1, PSRAM_CMD_QPI);
289 current_wrap_size = wrap_size;
290 return ESP_OK;
291 case 16:
292 case 64:
293 default:
294 return ESP_FAIL;
295 }
296 }
297
psram_support_wrap_size(uint32_t wrap_size)298 bool psram_support_wrap_size(uint32_t wrap_size)
299 {
300 switch (wrap_size) {
301 case 0:
302 case 32:
303 return true;
304 case 16:
305 case 64:
306 default:
307 return false;
308 }
309
310 }
311
312 //read psram id, should issue `psram_disable_qio_mode` before calling this
psram_read_id(int spi_num,uint32_t * dev_id)313 static void psram_read_id(int spi_num, uint32_t* dev_id)
314 {
315 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
316 PSRAM_DEVICE_ID, 8, /* command and command bit len*/
317 0, 24, /* address and address bit len*/
318 0, /* dummy bit len */
319 NULL, 0, /* tx data and tx bit len*/
320 (uint8_t*) dev_id, 24, /* rx data and rx bit len*/
321 CS_PSRAM_SEL, /* cs bit mask*/
322 false); /* whether is program/erase operation */
323 }
324
325 //enter QPI mode
psram_enable_qio_mode(int spi_num)326 static void IRAM_ATTR psram_enable_qio_mode(int spi_num)
327 {
328 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
329 PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
330 0, 0, /* address and address bit len*/
331 0, /* dummy bit len */
332 NULL, 0, /* tx data and tx bit len*/
333 NULL, 0, /* rx data and rx bit len*/
334 CS_PSRAM_SEL, /* cs bit mask*/
335 false); /* whether is program/erase operation */
336 }
337
psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode)338 static void psram_set_spi1_cmd_cs_timing(psram_clk_mode_t clk_mode)
339 {
340 if (clk_mode == PSRAM_CLK_MODE_NORM) {
341 // SPI1 Flash Operation port
342 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
343 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_FLASH_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
344 SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
345 } else {
346 SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_FLASH_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
347 }
348 }
349
psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode)350 static void psram_set_spi0_cache_cs_timing(psram_clk_mode_t clk_mode)
351 {
352 if (clk_mode == PSRAM_CLK_MODE_NORM) {
353 // SPI0 SRAM Cache port
354 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 1, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S);
355 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S);
356 SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(_SPI_CACHE_PORT), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M);
357 // SPI0 Flash Cache port
358 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
359 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(_SPI_CACHE_PORT), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
360 SET_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
361 } else {
362 CLEAR_PERI_REG_MASK(SPI_MEM_USER_REG(_SPI_CACHE_PORT), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
363 }
364 }
365
366 //psram gpio init , different working frequency we have different solutions
psram_gpio_config(psram_cache_speed_t mode)367 static void IRAM_ATTR psram_gpio_config(psram_cache_speed_t mode)
368 {
369 psram_io_t psram_io = PSRAM_IO_CONF_DEFAULT();
370 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
371 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
372 /* FLASH pins(except wp / hd) are all configured via IO_MUX in rom. */
373 } else {
374 // FLASH pins are all configured via GPIO matrix in ROM.
375 psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig);
376 psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig);
377 psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
378 psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig);
379 psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
380 psram_io.psram_spiwp_sd3_io = esp_rom_efuse_get_flash_wp_gpio();
381 }
382 esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig);
383 s_psram_cs_io = psram_io.psram_cs_io;
384
385 // Preserve psram pins
386 esp_gpio_reserve_pins(BIT64(psram_io.flash_clk_io) |
387 BIT64(psram_io.flash_cs_io) |
388 BIT64(psram_io.psram_clk_io) |
389 BIT64(psram_io.psram_cs_io) |
390 BIT64(psram_io.psram_spiq_sd0_io) |
391 BIT64(psram_io.psram_spid_sd1_io) |
392 BIT64(psram_io.psram_spihd_sd2_io) |
393 BIT64(psram_io.psram_spiwp_sd3_io) );
394 }
395
396 //used in UT only
psram_is_32mbit_ver0(void)397 bool psram_is_32mbit_ver0(void)
398 {
399 return PSRAM_IS_32MBIT_VER0(s_psram_id);
400 }
401
psram_set_clk_mode(int spi_num,psram_clk_mode_t clk_mode)402 static void psram_set_clk_mode(int spi_num, psram_clk_mode_t clk_mode)
403 {
404 if (spi_num == _SPI_CACHE_PORT) {
405 REG_SET_FIELD(SPI_MEM_SRAM_CMD_REG(0), SPI_MEM_SCLK_MODE, clk_mode);
406 } else if (spi_num == _SPI_FLASH_PORT) {
407 REG_SET_FIELD(SPI_MEM_CTRL1_REG(1), SPI_MEM_CLK_MODE, clk_mode);
408 }
409 }
410
411 /*
412 * Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
413 * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
414 */
esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)415 esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psram init
416 {
417 psram_cache_speed_t mode = PSRAM_SPEED;
418 assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
419 // GPIO related settings
420 psram_gpio_config(mode);
421
422 /* SPI1: set spi1 clk mode, in order to send commands on SPI1 */
423 /* SPI1: set cs timing(hold time) in order to send commands on SPI1 */
424 psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_A1C);
425 psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_A1C);
426
427 int spi_num = PSRAM_SPI_1;
428 psram_disable_qio_mode(spi_num);
429 psram_read_id(spi_num, &s_psram_id);
430 if (!PSRAM_IS_VALID(s_psram_id)) {
431 /* 16Mbit psram ID read error workaround:
432 * treat the first read id as a dummy one as the pre-condition,
433 * Send Read ID command again
434 */
435 psram_read_id(spi_num, &s_psram_id);
436 if (!PSRAM_IS_VALID(s_psram_id)) {
437 ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported", (uint32_t)s_psram_id);
438 return ESP_ERR_NOT_SUPPORTED;
439 }
440 }
441
442 psram_clk_mode_t clk_mode = PSRAM_CLK_MODE_MAX;
443 if (psram_is_32mbit_ver0()) {
444 clk_mode = PSRAM_CLK_MODE_A1C;
445 // SPI1: keep clock mode and cs timing for spi1
446 } else {
447 // For other psram, we don't need any extra clock cycles after cs get back to high level
448 clk_mode = PSRAM_CLK_MODE_NORM;
449 // SPI1: set clock mode and cs timing to normal mode
450 psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM);
451 psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM);
452 }
453
454 /* SPI1: send psram reset command */
455 /* SPI1: send QPI enable command */
456 psram_reset_mode(PSRAM_SPI_1);
457 psram_enable_qio_mode(PSRAM_SPI_1);
458
459 // after sending commands, set spi1 clock mode and cs timing to normal mode.
460 // since all the operations are sent via SPI0 Cache
461 /* SPI1: set clock mode to normal mode. */
462 /* SPI1: set cs timing to normal */
463 psram_set_clk_mode(_SPI_FLASH_PORT, PSRAM_CLK_MODE_NORM);
464 psram_set_spi1_cmd_cs_timing(PSRAM_CLK_MODE_NORM);
465
466 /* SPI0: set spi0 clock mode */
467 /* SPI0: set spi0 flash/cache cs timing */
468 psram_set_clk_mode(_SPI_CACHE_PORT, clk_mode);
469 psram_set_spi0_cache_cs_timing(clk_mode);
470
471 // SPI0: init SPI commands for Cache
472 psram_cache_init(mode, vaddrmode);
473
474 return ESP_OK;
475 }
476
psram_clock_set(int spi_num,int8_t freqdiv)477 static void IRAM_ATTR psram_clock_set(int spi_num, int8_t freqdiv)
478 {
479 uint32_t freqbits;
480 if (1 >= freqdiv) {
481 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
482 } else {
483 freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
484 WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
485 }
486 }
487
488 //register initialization for sram cache params and r/w commands
psram_cache_init(psram_cache_speed_t psram_cache_mode,psram_vaddr_mode_t vaddrmode)489 static void IRAM_ATTR psram_cache_init(psram_cache_speed_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
490 {
491 int extra_dummy = 0;
492 switch (psram_cache_mode) {
493 case PSRAM_CACHE_S80M:
494 psram_clock_set(0, 1);
495 extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
496 break;
497 case PSRAM_CACHE_S40M:
498 psram_clock_set(0, 2);
499 extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
500 break;
501 case PSRAM_CACHE_S26M:
502 psram_clock_set(0, 3);
503 extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
504 break;
505 case PSRAM_CACHE_S20M:
506 psram_clock_set(0, 4);
507 extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
508 break;
509 default:
510 psram_clock_set(0, 2);
511 break;
512 }
513
514 CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
515 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
516 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
517 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
518 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S); //write address for cache command.
519 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
520
521 //config sram cache r/w command
522 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
523 SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
524 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
525 SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
526 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
527 SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
528 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
529 SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
530 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
531 SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
532
533 #if !CONFIG_FREERTOS_UNICORE
534 DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
535 DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
536 if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
537 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
538 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
539 } else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
540 DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
541 DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
542 }
543 #endif
544
545 CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
546 }
547
548
549 /*---------------------------------------------------------------------------------
550 * Following APIs are not required to be IRAM-Safe
551 *
552 * Consider moving these to another file if this kind of APIs grows dramatically
553 *-------------------------------------------------------------------------------*/
esp_psram_impl_get_physical_size(uint32_t * out_size_bytes)554 esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
555 {
556 if (!out_size_bytes) {
557 return ESP_ERR_INVALID_ARG;
558 }
559
560 if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
561 *out_size_bytes = PSRAM_SIZE_8MB;
562 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) {
563 *out_size_bytes = PSRAM_SIZE_4MB;
564 } else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) {
565 *out_size_bytes = PSRAM_SIZE_2MB;
566 } else {
567 return ESP_ERR_NOT_SUPPORTED;
568 }
569 return ESP_OK;
570 }
571
572 /**
573 * This function is to get the available physical psram size in bytes.
574 * On ESP32S2, all of the PSRAM physical region are available
575 */
esp_psram_impl_get_available_size(uint32_t * out_size_bytes)576 esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
577 {
578 return esp_psram_impl_get_physical_size(out_size_bytes);
579 }
580
