1 /*
2 * SPDX-FileCopyrightText: 2013-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include "string.h"
9 #include "esp_attr.h"
10 #include "esp_err.h"
11 #include "esp_types.h"
12 #include "esp_bit_defs.h"
13 #include "esp_log.h"
14 #include "../esp_psram_impl.h"
15 #include "esp32s3/rom/spi_flash.h"
16 #include "esp32s3/rom/opi_flash.h"
17 #include "esp_rom_gpio.h"
18 #include "esp_rom_efuse.h"
19 #include "hal/gpio_hal.h"
20 #include "soc/rtc.h"
21 #include "esp_private/spi_flash_os.h"
22 #include "esp_private/mspi_timing_tuning.h"
23 #include "esp_private/esp_gpio_reserve.h"
24
25 static const char* TAG = "quad_psram";
26
27 //Commands for PSRAM chip
28 #define PSRAM_READ 0x03
29 #define PSRAM_FAST_READ 0x0B
30 #define PSRAM_FAST_READ_QUAD 0xEB
31 #define PSRAM_WRITE 0x02
32 #define PSRAM_QUAD_WRITE 0x38
33 #define PSRAM_ENTER_QMODE 0x35
34 #define PSRAM_EXIT_QMODE 0xF5
35 #define PSRAM_RESET_EN 0x66
36 #define PSRAM_RESET 0x99
37 #define PSRAM_SET_BURST_LEN 0xC0
38 #define PSRAM_DEVICE_ID 0x9F
39 #define PSRAM_MFR_ISSI_ID 0x9D
40
41 #define PSRAM_FAST_READ_DUMMY 4
42 #define PSRAM_FAST_READ_QUAD_DUMMY 6
43
44 // ID
45 #define PSRAM_ID_MFR_M 0xff
46 #define PSRAM_ID_KGD_M 0xff
47 #define PSRAM_ID_KGD_S 8
48 #define PSRAM_ID_KGD 0x5d
49 #define PSRAM_ID_EID_M 0xff
50 #define PSRAM_ID_EID_S 16
51
52 // Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
53 //
54 // BIT7 | BIT6 | BIT5 | SIZE(MBIT)
55 // -------------------------------------
56 // 0 | 0 | 0 | 16
57 // 0 | 0 | 1 | 32
58 // 0 | 1 | 0 | 64
59 //
60 // For ISSI Manufacturer the below table is used instead:
61 // BIT7 | BIT6 | BIT5 | SIZE(MBIT)
62 // -------------------------------------
63 // 0 | 0 | 0 | 8
64 // 0 | 0 | 1 | 16
65 // 0 | 1 | 0 | 32
66 #define PSRAM_EID_SIZE_M 0x07
67 #define PSRAM_EID_SIZE_S 5
68
69 #define PSRAM_MFR(id) ((id) & PSRAM_ID_MFR_M)
70 #define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
71 #define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
72 #define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
73 #define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
74
75 #define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
76
77 // IO-pins for PSRAM.
78 // WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
79 // hardcode the flash pins as well, making this code incompatible with either a setup
80 // that has the flash on non-standard pins or ESP32s with built-in flash.
81 #define FLASH_CLK_IO SPI_CLK_GPIO_NUM
82 #define FLASH_CS_IO SPI_CS0_GPIO_NUM
83 // PSRAM clock and cs IO should be configured based on hardware design.
84 #define PSRAM_CLK_IO SPI_CLK_GPIO_NUM
85 #define PSRAM_CS_IO SPI_CS1_GPIO_NUM
86 #define PSRAM_SPIQ_SD0_IO SPI_Q_GPIO_NUM
87 #define PSRAM_SPID_SD1_IO SPI_D_GPIO_NUM
88 #define PSRAM_SPIWP_SD3_IO SPI_WP_GPIO_NUM
89 #define PSRAM_SPIHD_SD2_IO SPI_HD_GPIO_NUM
90
91 #define CS_PSRAM_SEL SPI_MEM_CS1_DIS_M
92 #define CS_FLASH_SEL SPI_MEM_CS0_DIS_M
93
94 #define SPI1_NUM 1
95 #define SPI0_NUM 0
96
97 typedef enum {
98 PSRAM_CMD_QPI,
99 PSRAM_CMD_SPI,
100 } psram_cmd_mode_t;
101
102 typedef esp_rom_spi_cmd_t psram_cmd_t;
103
104 enum psram_manufacturer {
105 PSRAM_MNF_GENERIC = 0,
106 PSRAM_MNF_ISSI,
107 };
108
109 static enum psram_manufacturer s_psram_manufacturer;
110 static uint32_t s_psram_id = 0;
111 static uint32_t s_psram_size = 0; //this stands for physical psram size in bytes
112 static void config_psram_spi_phases(void);
113 extern void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
114
115 static uint8_t s_psram_cs_io = (uint8_t)-1;
116
esp_psram_impl_get_cs_io(void)117 uint8_t esp_psram_impl_get_cs_io(void)
118 {
119 return s_psram_cs_io;
120 }
121
psram_set_op_mode(int spi_num,psram_cmd_mode_t mode)122 static void psram_set_op_mode(int spi_num, psram_cmd_mode_t mode)
123 {
124 if (mode == PSRAM_CMD_QPI) {
125 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_QIO_MODE);
126 SET_PERI_REG_MASK(SPI_MEM_CTRL_REG(spi_num), SPI_MEM_FCMD_QUAD_M);
127 } else if (mode == PSRAM_CMD_SPI) {
128 esp_rom_spi_set_op_mode(spi_num, ESP_ROM_SPIFLASH_SLOWRD_MODE);
129 }
130 }
_psram_exec_cmd(int spi_num,uint32_t cmd,int cmd_bit_len,uint32_t addr,int addr_bit_len,int dummy_bits,uint8_t * mosi_data,int mosi_bit_len,uint8_t * miso_data,int miso_bit_len)131 static void _psram_exec_cmd(int spi_num,
132 uint32_t cmd, int cmd_bit_len,
133 uint32_t addr, int addr_bit_len,
134 int dummy_bits,
135 uint8_t* mosi_data, int mosi_bit_len,
136 uint8_t* miso_data, int miso_bit_len)
137 {
138 esp_rom_spi_cmd_t conf;
139 uint32_t _addr = addr;
140 conf.addr = &_addr;
141 conf.addrBitLen = addr_bit_len;
142 conf.cmd = cmd;
143 conf.cmdBitLen = cmd_bit_len;
144 conf.dummyBitLen = dummy_bits; // There is a hardware approach on chip723
145 conf.txData = (uint32_t*) mosi_data;
146 conf.txDataBitLen = mosi_bit_len;
147 conf.rxData = (uint32_t*) miso_data;
148 conf.rxDataBitLen = miso_bit_len;
149 esp_rom_spi_cmd_config(spi_num, &conf);
150 }
151
psram_exec_cmd(int spi_num,psram_cmd_mode_t mode,uint32_t cmd,int cmd_bit_len,uint32_t addr,int addr_bit_len,int dummy_bits,uint8_t * mosi_data,int mosi_bit_len,uint8_t * miso_data,int miso_bit_len,uint32_t cs_mask,bool is_write_erase_operation)152 void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
153 uint32_t cmd, int cmd_bit_len,
154 uint32_t addr, int addr_bit_len,
155 int dummy_bits,
156 uint8_t* mosi_data, int mosi_bit_len,
157 uint8_t* miso_data, int miso_bit_len,
158 uint32_t cs_mask,
159 bool is_write_erase_operation)
160 {
161 uint32_t backup_usr = READ_PERI_REG(SPI_MEM_USER_REG(spi_num));
162 uint32_t backup_usr1 = READ_PERI_REG(SPI_MEM_USER1_REG(spi_num));
163 uint32_t backup_usr2 = READ_PERI_REG(SPI_MEM_USER2_REG(spi_num));
164 uint32_t backup_ctrl = READ_PERI_REG(SPI_MEM_CTRL_REG(spi_num));
165 psram_set_op_mode(spi_num, mode);
166 _psram_exec_cmd(spi_num, cmd, cmd_bit_len, addr, addr_bit_len,
167 dummy_bits, mosi_data, mosi_bit_len, miso_data, miso_bit_len);
168 esp_rom_spi_cmd_start(spi_num, miso_data, miso_bit_len / 8, cs_mask, is_write_erase_operation);
169
170 WRITE_PERI_REG(SPI_MEM_USER_REG(spi_num), backup_usr);
171 WRITE_PERI_REG(SPI_MEM_USER1_REG(spi_num), backup_usr1);
172 WRITE_PERI_REG(SPI_MEM_USER2_REG(spi_num), backup_usr2);
173 WRITE_PERI_REG(SPI_MEM_CTRL_REG(spi_num), backup_ctrl);
174 }
175
176 //exit QPI mode(set back to SPI mode)
psram_disable_qio_mode(int spi_num)177 static void psram_disable_qio_mode(int spi_num)
178 {
179 psram_exec_cmd(spi_num, PSRAM_CMD_QPI,
180 PSRAM_EXIT_QMODE, 8, /* command and command bit len*/
181 0, 0, /* address and address bit len*/
182 0, /* dummy bit len */
183 NULL, 0, /* tx data and tx bit len*/
184 NULL, 0, /* rx data and rx bit len*/
185 CS_PSRAM_SEL, /* cs bit mask*/
186 false); /* whether is program/erase operation */
187 }
188
189 //TODO IDF-4307
190 //switch psram burst length(32 bytes or 1024 bytes)
191 //datasheet says it should be 1024 bytes by default
psram_set_wrap_burst_length(int spi_num,psram_cmd_mode_t mode)192 static void psram_set_wrap_burst_length(int spi_num, psram_cmd_mode_t mode)
193 {
194 psram_exec_cmd(spi_num, mode,
195 PSRAM_SET_BURST_LEN, 8, /* command and command bit len*/
196 0, 0, /* address and address bit len*/
197 0, /* dummy bit len */
198 NULL, 0, /* tx data and tx bit len*/
199 NULL, 0, /* rx data and rx bit len*/
200 CS_PSRAM_SEL, /* cs bit mask*/
201 false); /* whether is program/erase operation */
202 }
203
204 //send reset command to psram, in spi mode
psram_reset_mode(int spi_num)205 static void psram_reset_mode(int spi_num)
206 {
207 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
208 PSRAM_RESET_EN, 8, /* command and command bit len*/
209 0, 0, /* address and address bit len*/
210 0, /* dummy bit len */
211 NULL, 0, /* tx data and tx bit len*/
212 NULL, 0, /* rx data and rx bit len*/
213 CS_PSRAM_SEL, /* cs bit mask*/
214 false); /* whether is program/erase operation */
215
216 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
217 PSRAM_RESET, 8, /* command and command bit len*/
218 0, 0, /* address and address bit len*/
219 0, /* dummy bit len */
220 NULL, 0, /* tx data and tx bit len*/
221 NULL, 0, /* rx data and rx bit len*/
222 CS_PSRAM_SEL, /* cs bit mask*/
223 false); /* whether is program/erase operation */
224 }
225
psram_enable_wrap(uint32_t wrap_size)226 esp_err_t psram_enable_wrap(uint32_t wrap_size)
227 {
228 //TODO: IDF-4307
229 static uint32_t current_wrap_size = 0;
230 if (current_wrap_size == wrap_size) {
231 return ESP_OK;
232 }
233 switch (wrap_size) {
234 case 32:
235 case 0:
236 psram_set_wrap_burst_length(1, PSRAM_CMD_QPI);
237 current_wrap_size = wrap_size;
238 return ESP_OK;
239 case 16:
240 case 64:
241 default:
242 return ESP_FAIL;
243 }
244 }
245
psram_support_wrap_size(uint32_t wrap_size)246 bool psram_support_wrap_size(uint32_t wrap_size)
247 {
248 switch (wrap_size) {
249 case 0:
250 case 32:
251 return true;
252 case 16:
253 case 64:
254 default:
255 return false;
256 }
257
258 }
259
260 //Read ID operation only supports SPI CMD and mode, should issue `psram_disable_qio_mode` before calling this
psram_read_id(int spi_num,uint32_t * dev_id)261 static void psram_read_id(int spi_num, uint32_t* dev_id)
262 {
263 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
264 PSRAM_DEVICE_ID, 8, /* command and command bit len*/
265 0, 24, /* address and address bit len*/
266 0, /* dummy bit len */
267 NULL, 0, /* tx data and tx bit len*/
268 (uint8_t*) dev_id, 24, /* rx data and rx bit len*/
269 CS_PSRAM_SEL, /* cs bit mask*/
270 false); /* whether is program/erase operation */
271 }
272
273 //enter QPI mode
psram_enable_qio_mode(int spi_num)274 static void psram_enable_qio_mode(int spi_num)
275 {
276 psram_exec_cmd(spi_num, PSRAM_CMD_SPI,
277 PSRAM_ENTER_QMODE, 8, /* command and command bit len*/
278 0, 0, /* address and address bit len*/
279 0, /* dummy bit len */
280 NULL, 0, /* tx data and tx bit len*/
281 NULL, 0, /* rx data and rx bit len*/
282 CS_PSRAM_SEL, /* cs bit mask*/
283 false); /* whether is program/erase operation */
284 }
285
psram_set_cs_timing(void)286 static void psram_set_cs_timing(void)
287 {
288 //SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time registers for PSRAM, so we only need to set SPI0 related registers here
289 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S);
290 SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V, 0, SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S);
291 SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_AC_REG(0), SPI_MEM_SPI_SMEM_CS_HOLD_M | SPI_MEM_SPI_SMEM_CS_SETUP_M);
292 }
293
psram_gpio_config(void)294 static void psram_gpio_config(void)
295 {
296 //CS1
297 uint8_t cs1_io = PSRAM_CS_IO;
298 if (cs1_io == SPI_CS1_GPIO_NUM) {
299 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], FUNC_SPICS1_SPICS1);
300 } else {
301 esp_rom_gpio_connect_out_signal(cs1_io, SPICS1_OUT_IDX, 0, 0);
302 gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[cs1_io], PIN_FUNC_GPIO);
303 }
304 s_psram_cs_io = cs1_io;
305
306 //WP HD
307 uint8_t wp_io = PSRAM_SPIWP_SD3_IO;
308 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
309 if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
310 // MSPI pins (except wp / hd) are all configured via IO_MUX in 1st bootloader.
311 } else {
312 // MSPI pins (except wp / hd) are all configured via GPIO matrix in 1st bootloader.
313 wp_io = esp_rom_efuse_get_flash_wp_gpio();
314 }
315 //This ROM function will init both WP and HD pins.
316 esp_rom_spiflash_select_qio_pins(wp_io, spiconfig);
317
318 // Reserve psram pins
319 esp_gpio_reserve_pins(BIT64(cs1_io) | BIT64(wp_io));
320 }
321
esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)322 esp_err_t esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psram init
323 {
324 const uint32_t psram_size_lut[][3] = {
325 [PSRAM_MNF_GENERIC] =
326 {
327 PSRAM_SIZE_2MB,
328 PSRAM_SIZE_4MB,
329 PSRAM_SIZE_8MB,
330 },
331 [PSRAM_MNF_ISSI] =
332 {
333 PSRAM_SIZE_1MB,
334 PSRAM_SIZE_2MB,
335 PSRAM_SIZE_4MB,
336 },
337 };
338
339 psram_gpio_config();
340 psram_set_cs_timing();
341
342 //enter MSPI slow mode to init PSRAM device registers
343 mspi_timing_enter_low_speed_mode(true);
344
345 //We use SPI1 to init PSRAM
346 psram_disable_qio_mode(SPI1_NUM);
347 psram_read_id(SPI1_NUM, &s_psram_id);
348 if (!PSRAM_IS_VALID(s_psram_id)) {
349 /* 16Mbit psram ID read error workaround:
350 * treat the first read id as a dummy one as the pre-condition,
351 * Send Read ID command again
352 */
353 psram_read_id(SPI1_NUM, &s_psram_id);
354 if (!PSRAM_IS_VALID(s_psram_id)) {
355 ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
356 return ESP_ERR_NOT_SUPPORTED;
357 }
358 }
359
360 if (PSRAM_MFR(s_psram_id) == PSRAM_MFR_ISSI_ID) {
361 s_psram_manufacturer = PSRAM_MNF_ISSI;
362 } else {
363 s_psram_manufacturer = PSRAM_MNF_GENERIC;
364 }
365
366 if (PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
367 s_psram_size = PSRAM_SIZE_8MB;
368 } else {
369 uint8_t density = PSRAM_SIZE_ID(s_psram_id);
370 if (density >= 0b11) {
371 s_psram_size = 0;
372 } else {
373 s_psram_size = psram_size_lut[s_psram_manufacturer][density];
374 }
375 }
376
377 //SPI1: send psram reset command
378 psram_reset_mode(SPI1_NUM);
379 //SPI1: send QPI enable command
380 psram_enable_qio_mode(SPI1_NUM);
381
382 //Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
383 mspi_timing_psram_tuning();
384
385 //Configure SPI0 PSRAM related SPI Phases
386 config_psram_spi_phases();
387 //Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
388 mspi_timing_enter_high_speed_mode(true);
389
390 return ESP_OK;
391 }
392
393 //Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
config_psram_spi_phases(void)394 static void config_psram_spi_phases(void)
395 {
396 //Config CMD phase
397 CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M); //disable dio mode for cache command
398 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M); //enable qio mode for cache command
399 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M); //enable cache read command
400 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M); //enable cache write command
401 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
402 SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
403 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
404 SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
405
406 //Config ADDR phase
407 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S);
408
409 //Dummy
410 /**
411 * We set the PSRAM chip required dummy here. If timing tuning is needed,
412 * the dummy length will be updated in `mspi_timing_enter_high_speed_mode()`
413 */
414 SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
415 SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy
416
417 CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
418 }
419
420
421 /*---------------------------------------------------------------------------------
422 * Following APIs are not required to be IRAM-Safe
423 *
424 * Consider moving these to another file if this kind of APIs grows dramatically
425 *-------------------------------------------------------------------------------*/
esp_psram_impl_get_physical_size(uint32_t * out_size_bytes)426 esp_err_t esp_psram_impl_get_physical_size(uint32_t *out_size_bytes)
427 {
428 if (!out_size_bytes) {
429 return ESP_ERR_INVALID_ARG;
430 }
431
432 *out_size_bytes = s_psram_size;
433 return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
434 }
435
436 /**
437 * This function is to get the available physical psram size in bytes.
438 *
439 * When ECC is enabled, the available size will be reduced.
440 * On S3 Quad PSRAM, ECC is not enabled for now.
441 */
esp_psram_impl_get_available_size(uint32_t * out_size_bytes)442 esp_err_t esp_psram_impl_get_available_size(uint32_t *out_size_bytes)
443 {
444 if (!out_size_bytes) {
445 return ESP_ERR_INVALID_ARG;
446 }
447
448 *out_size_bytes = s_psram_size;
449 return (s_psram_size ? ESP_OK : ESP_ERR_INVALID_STATE);
450 }
451
