1 /*
2 * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "sdkconfig.h"
8 #include "soc/spi_periph.h"
9 #include "esp_rom_spiflash.h"
10 #if CONFIG_IDF_TARGET_ESP32
11 #include "esp32/rom/spi_flash.h"
12 #elif CONFIG_IDF_TARGET_ESP32S2
13 #include "esp32s2/rom/spi_flash.h"
14 #elif CONFIG_IDF_TARGET_ESP32S3
15 #include "esp32s3/rom/spi_flash.h"
16 #include "esp32s3/rom/opi_flash.h"
17 #endif
18
19 #define SPI_IDX 1
20
21 #if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
22
23 #if CONFIG_IDF_TARGET_ESP32
24
25 extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
26
is_issi_chip(const esp_rom_spiflash_chip_t * chip)27 static inline bool is_issi_chip(const esp_rom_spiflash_chip_t* chip)
28 {
29 return (((chip->device_id >> 16)&0xff) == 0x9D);
30 }
31
esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t * spi)32 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi)
33 {
34 uint32_t status;
35 //wait for spi control ready
36 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
37 }
38 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
39 }
40 //wait for flash status ready
41 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_status(spi, &status)) {
42 return ESP_ROM_SPIFLASH_RESULT_ERR;
43 }
44 return ESP_ROM_SPIFLASH_RESULT_OK;
45 }
46
47 /* Modified version of esp_rom_spiflash_clear_bp() that replaces version in ROM.
48
49 This works around a bug where esp_rom_spiflash_clear_bp sometimes reads the wrong
50 high status byte (RDSR2 result) and then copies it back to the
51 flash status, which can cause the CMP bit or Status Register
52 Protect bit to become set.
53
54 Like other ROM SPI functions, this function is not designed to be
55 called directly from an RTOS environment without taking precautions
56 about interrupts, CPU coordination, flash mapping. However some of
57 the functions in esp_spi_flash.c call it.
58 */
esp_rom_spiflash_clear_bp(void)59 __attribute__((__unused__)) esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void)
60 {
61 uint32_t status;
62 uint32_t new_status;
63
64 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
65
66 if (is_issi_chip(&g_rom_spiflash_chip)) {
67 // ISSI chips have different QE position
68
69 if (esp_rom_spiflash_read_status(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) {
70 return ESP_ROM_SPIFLASH_RESULT_ERR;
71 }
72
73 /* Clear all bits in the mask.
74 (This is different from ROM esp_rom_spiflash_clear_bp, which keeps all bits as-is.)
75 */
76 new_status = status & (~ESP_ROM_SPIFLASH_BP_MASK_ISSI);
77 // Skip if nothing needs to be cleared. Otherwise will waste time waiting for the flash to clear nothing.
78 if (new_status == status) return ESP_ROM_SPIFLASH_RESULT_OK;
79
80 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B);
81 } else {
82 if (esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status) != ESP_ROM_SPIFLASH_RESULT_OK) {
83 return ESP_ROM_SPIFLASH_RESULT_ERR;
84 }
85
86 /* Clear all bits except QE, if it is set.
87 (This is different from ROM esp_rom_spiflash_clear_bp, which keeps all bits as-is.)
88 */
89 new_status = status & ESP_ROM_SPIFLASH_QE;
90 SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B);
91 }
92
93 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
94 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WREN);
95 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) {
96 }
97 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
98 esp_rom_spiflash_result_t ret = esp_rom_spiflash_write_status(&g_rom_spiflash_chip, new_status);
99 // WEL bit should be cleared after operations regardless of writing succeed or not.
100 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
101 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WRDI);
102 while (REG_READ(SPI_CMD_REG(SPI_IDX)) != 0) {
103 }
104 return ret;
105 }
106 esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void) __attribute__((alias("esp_rom_spiflash_clear_bp")));
107
108 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi);
109
110 //only support spi1
esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t * spi)111 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip_internal(esp_rom_spiflash_chip_t *spi)
112 {
113 esp_rom_spiflash_wait_idle(spi);
114
115 // Chip erase.
116 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE);
117 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
118 }
119
120 // check erase is finished.
121 esp_rom_spiflash_wait_idle(spi);
122
123 return ESP_ROM_SPIFLASH_RESULT_OK;
124 }
125
126 //only support spi1
esp_rom_spiflash_erase_sector_internal(esp_rom_spiflash_chip_t * spi,uint32_t addr)127 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
128 {
129 //check if addr is 4k alignment
130 if (0 != (addr & 0xfff)) {
131 return ESP_ROM_SPIFLASH_RESULT_ERR;
132 }
133
134 esp_rom_spiflash_wait_idle(spi);
135
136 // sector erase 4Kbytes erase is sector erase.
137 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
138 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE);
139 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
140 }
141
142 esp_rom_spiflash_wait_idle(spi);
143
144 return ESP_ROM_SPIFLASH_RESULT_OK;
145 }
146
147 //only support spi1
esp_rom_spiflash_erase_block_internal(esp_rom_spiflash_chip_t * spi,uint32_t addr)148 static esp_rom_spiflash_result_t esp_rom_spiflash_erase_block_internal(esp_rom_spiflash_chip_t *spi, uint32_t addr)
149 {
150 esp_rom_spiflash_wait_idle(spi);
151
152 // sector erase 4Kbytes erase is sector erase.
153 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
154 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE);
155 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
156 }
157
158 esp_rom_spiflash_wait_idle(spi);
159
160 return ESP_ROM_SPIFLASH_RESULT_OK;
161 }
162
163 //only support spi1
esp_rom_spiflash_program_page_internal(esp_rom_spiflash_chip_t * spi,uint32_t spi_addr,uint32_t * addr_source,int32_t byte_length)164 static esp_rom_spiflash_result_t esp_rom_spiflash_program_page_internal(esp_rom_spiflash_chip_t *spi, uint32_t spi_addr,
165 uint32_t *addr_source, int32_t byte_length)
166 {
167 uint32_t temp_addr;
168 int32_t temp_bl;
169 uint8_t i;
170 uint8_t remain_word_num;
171
172 //check 4byte alignment
173 if (0 != (byte_length & 0x3)) {
174 return ESP_ROM_SPIFLASH_RESULT_ERR;
175 }
176
177 //check if write in one page
178 if ((spi->page_size) < ((spi_addr % (spi->page_size)) + byte_length)) {
179 return ESP_ROM_SPIFLASH_RESULT_ERR;
180 }
181
182 esp_rom_spiflash_wait_idle(spi);
183
184 temp_addr = spi_addr;
185 temp_bl = byte_length;
186
187 while (temp_bl > 0 ) {
188 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(spi)) {
189 return ESP_ROM_SPIFLASH_RESULT_ERR;
190 }
191 if ( temp_bl >= ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM ) {
192 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM << ESP_ROM_SPIFLASH_BYTES_LEN )); // 32 byte a block
193
194 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM >> 2); i++) {
195 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
196 }
197 temp_bl = temp_bl - 32;
198 temp_addr = temp_addr + 32;
199 } else {
200 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES_LEN ));
201
202 remain_word_num = (0 == (temp_bl & 0x3)) ? (temp_bl >> 2) : (temp_bl >> 2) + 1;
203 for (i = 0; i < remain_word_num; i++) {
204 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++);
205 temp_bl = temp_bl - 4;
206 }
207 temp_bl = 0;
208 }
209 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP);
210 while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 ) {
211 }
212
213 esp_rom_spiflash_wait_idle(spi);
214 }
215
216 return ESP_ROM_SPIFLASH_RESULT_OK;
217 }
218
esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t * spi,uint32_t * status)219 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status)
220 {
221 uint32_t status_value = ESP_ROM_SPIFLASH_BUSY_FLAG;
222
223 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
224 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
225 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter
226 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDSR);
227 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
228 }
229
230 status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask);
231 }
232 } else {
233 while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
234 esp_rom_spiflash_read_user_cmd(&status_value, 0x05);
235 }
236 }
237 *status = status_value;
238
239 return ESP_ROM_SPIFLASH_RESULT_OK;
240 }
241
esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t * spi,uint32_t * status)242 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status)
243 {
244 esp_rom_spiflash_result_t ret;
245 esp_rom_spiflash_wait_idle(&g_rom_spiflash_chip);
246 ret = esp_rom_spiflash_read_user_cmd(status, 0x35);
247 *status = *status << 8;
248 return ret;
249 }
250
esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t * spi,uint32_t status_value)251 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value)
252 {
253 esp_rom_spiflash_wait_idle(spi);
254
255 // update status value by status_value
256 WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, status_value); // write status regisrter
257 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WRSR);
258 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
259 }
260 esp_rom_spiflash_wait_idle(spi);
261
262 return ESP_ROM_SPIFLASH_RESULT_OK;
263 }
264
265 //only support spi1
esp_rom_spiflash_read_data(esp_rom_spiflash_chip_t * spi,uint32_t flash_addr,uint32_t * addr_dest,int32_t byte_length)266 static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chip_t *spi, uint32_t flash_addr,
267 uint32_t *addr_dest, int32_t byte_length)
268 {
269 uint32_t temp_addr;
270 int32_t temp_length;
271 uint8_t i;
272 uint8_t remain_word_num;
273
274 //address range check
275 if ((flash_addr + byte_length) > (spi->chip_size)) {
276 return ESP_ROM_SPIFLASH_RESULT_ERR;
277 }
278
279 temp_addr = flash_addr;
280 temp_length = byte_length;
281
282 esp_rom_spiflash_wait_idle(spi);
283
284 while (temp_length > 0) {
285 if (temp_length >= ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM) {
286 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << ESP_ROM_SPIFLASH_BYTES_LEN));
287 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
288 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
289 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
290 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0) {
291 }
292
293 for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM >> 2); i++) {
294 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
295 }
296 temp_length = temp_length - ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
297 temp_addr = temp_addr + ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM;
298 } else {
299 //WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr |(temp_length << ESP_ROM_SPIFLASH_BYTES_LEN ));
300 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
301 REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
302 REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
303 while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0) {
304 };
305
306 remain_word_num = (0 == (temp_length & 0x3)) ? (temp_length >> 2) : (temp_length >> 2) + 1;
307 for (i = 0; i < remain_word_num; i++) {
308 *addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
309 }
310 temp_length = 0;
311 }
312 }
313
314 return ESP_ROM_SPIFLASH_RESULT_OK;
315 }
316
esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t * spi)317 static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi)
318 {
319 uint32_t flash_status = 0;
320
321 esp_rom_spiflash_wait_idle(spi);
322
323 //enable write
324 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WREN); // enable write operation
325 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
326 }
327
328 // make sure the flash is ready for writing
329 while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) {
330 esp_rom_spiflash_read_status(spi, &flash_status);
331 }
332
333 return ESP_ROM_SPIFLASH_RESULT_OK;
334 }
335
spi_cache_mode_switch(uint32_t modebit)336 static void spi_cache_mode_switch(uint32_t modebit)
337 {
338 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
339 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
340 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
341 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_QIO_ADDR_BITSLEN);
342 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
343 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xEB);
344 } else if (modebit & SPI_FASTRD_MODE) {
345 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
346 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
347 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_FAST_ADDR_BITSLEN);
348 if ((modebit & SPI_FREAD_QUAD)) {
349 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x6B);
350 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
351 } else if ((modebit & SPI_FREAD_DIO)) {
352 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_DIO_ADDR_BITSLEN);
353 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_DIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
354 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0xBB);
355 } else if ((modebit & SPI_FREAD_DUAL)) {
356 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
357 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x3B);
358 } else {
359 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, SPI0_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[0]);
360 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x0B);
361 }
362 } else {
363 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_MOSI);
364 if (g_rom_spiflash_dummy_len_plus[0] == 0) {
365 REG_CLR_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
366 } else {
367 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_DUMMY);
368 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[0] - 1);
369 }
370 REG_SET_BIT(SPI_USER_REG(0), SPI_USR_MISO | SPI_USR_ADDR);
371 REG_SET_FIELD(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN, SPI0_R_SIO_ADDR_BITSLEN);
372 REG_SET_FIELD(SPI_USER2_REG(0), SPI_USR_COMMAND_VALUE, 0x03);
373 }
374 }
375
esp_rom_spiflash_set_bp(void)376 esp_rom_spiflash_result_t esp_rom_spiflash_set_bp(void)
377 {
378 uint32_t status;
379
380 //read QE bit, not write if not QE
381 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_statushigh(&g_rom_spiflash_chip, &status)) {
382 return ESP_ROM_SPIFLASH_RESULT_ERR;
383 }
384 //enable 2 byte status writing
385 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN);
386
387 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
388 return ESP_ROM_SPIFLASH_RESULT_ERR;
389 }
390
391 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_write_status(&g_rom_spiflash_chip, status | ESP_ROM_SPIFLASH_WR_PROTECT)) {
392 return ESP_ROM_SPIFLASH_RESULT_ERR;
393 }
394
395 return ESP_ROM_SPIFLASH_RESULT_OK;
396 }
397 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void) __attribute__((alias("esp_rom_spiflash_set_bp")));
398
esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode)399 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode)
400 {
401 uint32_t modebit;
402 while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
403 }
404 while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
405 }
406 //clear old mode bit
407 CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
408 CLEAR_PERI_REG_MASK(SPI_CTRL_REG(0), SPI_FREAD_QIO | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_DUAL | SPI_FASTRD_MODE);
409 //configure read mode
410 switch (mode) {
411 case ESP_ROM_SPIFLASH_QIO_MODE : modebit = SPI_FREAD_QIO | SPI_FASTRD_MODE; break;
412 case ESP_ROM_SPIFLASH_QOUT_MODE : modebit = SPI_FREAD_QUAD | SPI_FASTRD_MODE; break;
413 case ESP_ROM_SPIFLASH_DIO_MODE : modebit = SPI_FREAD_DIO | SPI_FASTRD_MODE; break;
414 case ESP_ROM_SPIFLASH_DOUT_MODE : modebit = SPI_FREAD_DUAL | SPI_FASTRD_MODE; break;
415 case ESP_ROM_SPIFLASH_FASTRD_MODE: modebit = SPI_FASTRD_MODE; break;
416 case ESP_ROM_SPIFLASH_SLOWRD_MODE: modebit = 0; break;
417 default : modebit = 0;
418 }
419
420 SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL, modebit);
421 SET_PERI_REG_MASK(SPI_CTRL_REG(0), modebit);
422 spi_cache_mode_switch(modebit);
423
424 return ESP_ROM_SPIFLASH_RESULT_OK;
425 }
426
esp_rom_spiflash_erase_chip(void)427 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void)
428 {
429 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
430 return ESP_ROM_SPIFLASH_RESULT_ERR;
431 }
432
433 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_chip_internal(&g_rom_spiflash_chip)) {
434 return ESP_ROM_SPIFLASH_RESULT_ERR;
435 }
436
437 return ESP_ROM_SPIFLASH_RESULT_OK;
438 }
439
esp_rom_spiflash_erase_block(uint32_t block_num)440 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num)
441 {
442 // flash write is always 1 line currently
443 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
444 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
445 //check program size
446 if (block_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.block_size))) {
447 return ESP_ROM_SPIFLASH_RESULT_ERR;
448 }
449
450 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
451 return ESP_ROM_SPIFLASH_RESULT_ERR;
452 }
453
454 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block_internal(&g_rom_spiflash_chip, block_num * (g_rom_spiflash_chip.block_size))) {
455 return ESP_ROM_SPIFLASH_RESULT_ERR;
456 }
457 return ESP_ROM_SPIFLASH_RESULT_OK;
458 }
459
esp_rom_spiflash_erase_sector(uint32_t sector_num)460 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num)
461 {
462 // flash write is always 1 line currently
463 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
464 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
465 //check program size
466 if (sector_num >= ((g_rom_spiflash_chip.chip_size) / (g_rom_spiflash_chip.sector_size))) {
467 return ESP_ROM_SPIFLASH_RESULT_ERR;
468 }
469
470 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_enable_write(&g_rom_spiflash_chip)) {
471 return ESP_ROM_SPIFLASH_RESULT_ERR;
472 }
473
474 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector_internal(&g_rom_spiflash_chip, sector_num * (g_rom_spiflash_chip.sector_size))) {
475 return ESP_ROM_SPIFLASH_RESULT_ERR;
476 }
477
478 return ESP_ROM_SPIFLASH_RESULT_OK;
479 }
480
esp_rom_spiflash_write(uint32_t dest_addr,const uint32_t * src,int32_t len)481 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len)
482 {
483 uint32_t page_size;
484 uint32_t pgm_len;
485 uint32_t pgm_num;
486 uint32_t i;
487
488 // flash write is always 1 line currently
489 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
490 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
491 //check program size
492 if ( (dest_addr + len) > (g_rom_spiflash_chip.chip_size)) {
493 return ESP_ROM_SPIFLASH_RESULT_ERR;
494 }
495
496 page_size = g_rom_spiflash_chip.page_size;
497 pgm_len = page_size - (dest_addr % page_size);
498 if (len < pgm_len) {
499 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
500 dest_addr, (uint32_t *)src, len)) {
501 return ESP_ROM_SPIFLASH_RESULT_ERR;
502 }
503 } else {
504 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
505 dest_addr, (uint32_t *)src, pgm_len)) {
506 return ESP_ROM_SPIFLASH_RESULT_ERR;
507 }
508
509 //whole page program
510 pgm_num = (len - pgm_len) / page_size;
511 for (i = 0; i < pgm_num; i++) {
512 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
513 dest_addr + pgm_len, (uint32_t *)src + (pgm_len >> 2), page_size)) {
514 return ESP_ROM_SPIFLASH_RESULT_ERR;
515 }
516 pgm_len += page_size;
517 }
518
519 //remain parts to program
520 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
521 dest_addr + pgm_len, (uint32_t *)src + (pgm_len >> 2), len - pgm_len)) {
522 return ESP_ROM_SPIFLASH_RESULT_ERR;
523 }
524 }
525 return ESP_ROM_SPIFLASH_RESULT_OK;
526 }
527
esp_rom_spiflash_write_encrypted(uint32_t flash_addr,uint32_t * data,uint32_t len)528 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len)
529 {
530 esp_rom_spiflash_result_t ret = ESP_ROM_SPIFLASH_RESULT_OK;
531 uint32_t i;
532
533 if ((flash_addr & 0x1f) || (len & 0x1f)) { //check 32 byte alignment
534 return ESP_ROM_SPIFLASH_RESULT_ERR;
535 }
536
537 esp_rom_spiflash_write_encrypted_enable();
538
539 for (i = 0; i < (len >> 5); i++) {
540 if ((ret = esp_rom_spiflash_prepare_encrypted_data(flash_addr + (i << 5), data + (i << 3))) != ESP_ROM_SPIFLASH_RESULT_OK) {
541 break;
542 }
543
544 if ((ret = esp_rom_spiflash_write(flash_addr + (i << 5), data, 32)) != ESP_ROM_SPIFLASH_RESULT_OK) {
545 break;
546 }
547 }
548
549 esp_rom_spiflash_write_encrypted_disable();
550
551 return ret;
552 }
553
esp_rom_spiflash_read(uint32_t src_addr,uint32_t * dest,int32_t len)554 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len)
555 {
556 // QIO or SIO, non-QIO regard as SIO
557 uint32_t modebit;
558 modebit = READ_PERI_REG(PERIPHS_SPI_FLASH_CTRL);
559 if ((modebit & SPI_FREAD_QIO) && (modebit & SPI_FASTRD_MODE)) {
560 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
561 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR);
562 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_QIO_ADDR_BITSLEN);
563 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_QIO_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
564 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xEB);
565 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xEB);
566 } else if (modebit & SPI_FASTRD_MODE) {
567 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
568 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
569 if (modebit & SPI_FREAD_DIO) {
570 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
571 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
572 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
573 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0xBB);
574 } else {
575 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
576 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_DIO_ADDR_BITSLEN);
577 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
578 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0xBB);
579 }
580 } else {
581 if ((modebit & SPI_FREAD_QUAD)) {
582 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x6B);
583 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x6B);
584 } else if ((modebit & SPI_FREAD_DUAL)) {
585 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x3B);
586 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x3B);
587 } else {
588 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x0B);
589 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x0B);
590 }
591 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
592 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_FAST_ADDR_BITSLEN);
593 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, SPI1_R_FAST_DUMMY_CYCLELEN + g_rom_spiflash_dummy_len_plus[1]);
594 }
595 } else {
596 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MOSI);
597 if (g_rom_spiflash_dummy_len_plus[1] == 0) {
598 REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
599 } else {
600 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
601 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_DUMMY_CYCLELEN, g_rom_spiflash_dummy_len_plus[1] - 1);
602 }
603 REG_SET_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_MISO | SPI_USR_ADDR);
604 REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, SPI1_R_SIO_ADDR_BITSLEN);
605 //REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG2, SPI_USR_COMMAND_VALUE, 0x03);
606 REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x03);
607 }
608
609 if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_data(&g_rom_spiflash_chip, src_addr, dest, len)) {
610 return ESP_ROM_SPIFLASH_RESULT_ERR;
611 }
612 return ESP_ROM_SPIFLASH_RESULT_OK;
613 }
614
esp_rom_spiflash_erase_area(uint32_t start_addr,uint32_t area_len)615 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len)
616 {
617 int32_t total_sector_num;
618 int32_t head_sector_num;
619 uint32_t sector_no;
620 uint32_t sector_num_per_block;
621
622 //set read mode to Fastmode ,not QDIO mode for erase
623 //
624 // TODO: this is probably a bug as it doesn't re-enable QIO mode, not serious as this
625 // function is not used in IDF.
626 esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE);
627
628 //check if area is oversize of flash
629 if ((start_addr + area_len) > g_rom_spiflash_chip.chip_size) {
630 return ESP_ROM_SPIFLASH_RESULT_ERR;
631 }
632
633 //start_addr is aligned as sector boundary
634 if (0 != (start_addr % g_rom_spiflash_chip.sector_size)) {
635 return ESP_ROM_SPIFLASH_RESULT_ERR;
636 }
637
638 //Unlock flash to enable erase
639 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_clear_bp(/*&g_rom_spiflash_chip*/)) {
640 return ESP_ROM_SPIFLASH_RESULT_ERR;
641 }
642
643 sector_no = start_addr / g_rom_spiflash_chip.sector_size;
644 sector_num_per_block = g_rom_spiflash_chip.block_size / g_rom_spiflash_chip.sector_size;
645 total_sector_num = (0 == (area_len % g_rom_spiflash_chip.sector_size)) ? area_len / g_rom_spiflash_chip.sector_size :
646 1 + (area_len / g_rom_spiflash_chip.sector_size);
647
648 //check if erase area reach over block boundary
649 head_sector_num = sector_num_per_block - (sector_no % sector_num_per_block);
650
651 head_sector_num = (head_sector_num >= total_sector_num) ? total_sector_num : head_sector_num;
652
653 //JJJ, BUG of 6.0 erase
654 //middle part of area is aligned by blocks
655 total_sector_num -= head_sector_num;
656
657 //head part of area is erased
658 while (0 != head_sector_num) {
659 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
660 return ESP_ROM_SPIFLASH_RESULT_ERR;
661 }
662 sector_no++;
663 head_sector_num--;
664 }
665 while (total_sector_num > sector_num_per_block) {
666 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_block(sector_no / sector_num_per_block)) {
667 return ESP_ROM_SPIFLASH_RESULT_ERR;
668 }
669 sector_no += sector_num_per_block;
670 total_sector_num -= sector_num_per_block;
671 }
672
673 //tail part of area burn
674 while (0 < total_sector_num) {
675 if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_erase_sector(sector_no)) {
676 return ESP_ROM_SPIFLASH_RESULT_ERR;
677 }
678 sector_no++;
679 total_sector_num--;
680 }
681
682 return ESP_ROM_SPIFLASH_RESULT_OK;
683 }
684
esp_rom_spiflash_write_disable(void)685 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
686 {
687 REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WRDI);
688 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
689 }
690 return ESP_ROM_SPIFLASH_RESULT_OK;
691 }
692
693 #elif CONFIG_IDF_TARGET_ESP32S2
694
esp_rom_spiflash_write_disable(void)695 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
696 {
697 REG_WRITE(SPI_MEM_CMD_REG(SPI_IDX), SPI_MEM_FLASH_WRDI);
698 while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
699 }
700 return ESP_ROM_SPIFLASH_RESULT_OK;
701 }
702
703 #elif CONFIG_IDF_TARGET_ESP32S3
704 extern void esp_rom_spi_set_address_bit_len(int spi, int addr_bits);
esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode,const esp_rom_opiflash_spi0rd_t * cache)705 void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache)
706 {
707 esp_rom_spi_set_op_mode(0, mode);
708 REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MOSI);
709 REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_MISO | SPI_MEM_USR_ADDR);
710
711 if (cache) {
712 esp_rom_spi_set_address_bit_len(0, cache->addr_bit_len);
713 // Patch for ROM function `esp_rom_opiflash_cache_mode_config`, because when dummy is 0,
714 // `SPI_MEM_USR_DUMMY` should be 0. `esp_rom_opiflash_cache_mode_config` doesn't handle this
715 // properly.
716 if (cache->dummy_bit_len == 0) {
717 REG_CLR_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
718 } else {
719 REG_SET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_USR_DUMMY);
720 REG_SET_FIELD(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN, cache->dummy_bit_len - 1 + rom_spiflash_legacy_data->dummy_len_plus[0]);
721 }
722 REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_VALUE, cache->cmd);
723 REG_SET_FIELD(SPI_MEM_USER2_REG(0), SPI_MEM_USR_COMMAND_BITLEN, cache->cmd_bit_len - 1);
724 REG_SET_FIELD(SPI_MEM_DDR_REG(0), SPI_MEM_SPI_FMEM_VAR_DUMMY, cache->var_dummy_en);
725 }
726 }
727
728 #endif // IDF_TARGET
729
730 #endif // CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
731
