1 /*
2  * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <stdlib.h>
8 #include <string.h>
9 #include <stdio.h>
10 #include <sys/param.h>
11 
12 #include "flash_init.h"
13 #include "soc_flash_init.h"
14 
15 #include "soc/io_mux_reg.h"
16 #include "esp_log.h"
17 #include "bootloader_flash_priv.h"
18 #include "bootloader_flash_config.h"
19 #include "esp_rom_efuse.h"
20 #include "esp_rom_gpio.h"
21 #include "flash_qio_mode.h"
22 
23 #include "hal/cache_ll.h"
24 #include "hal/cache_hal.h"
25 
26 #define FLASH_IO_MATRIX_DUMMY_40M       0
27 #define FLASH_IO_MATRIX_DUMMY_80M       0
28 #define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3
29 #define FLASH_CS_SETUP_TIME             3
30 #define FLASH_CS_HOLD_TIME              3
31 #define FLASH_CS_HOLD_DELAY             2
32 
33 #define TAG "flash_init"
34 
35 extern esp_image_header_t bootloader_image_hdr;
36 
configure_spi_pins(int drv)37 void configure_spi_pins(int drv)
38 {
39 	const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
40 	uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
41 	uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
42 	uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
43 	uint8_t d_gpio_num = SPI_D_GPIO_NUM;
44 	uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
45 	uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
46 	uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
47 
48 	if (spiconfig == 0) {
49 
50 	} else {
51 		clk_gpio_num = spiconfig & 0x3f;
52 		q_gpio_num = (spiconfig >> 6) & 0x3f;
53 		d_gpio_num = (spiconfig >> 12) & 0x3f;
54 		cs0_gpio_num = (spiconfig >> 18) & 0x3f;
55 		hd_gpio_num = (spiconfig >> 24) & 0x3f;
56 		wp_gpio_num = wp_pin;
57 	}
58 	esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
59 	esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
60 	esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
61 	esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
62 	if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
63 		esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
64 	}
65 	if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
66 		esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
67 	}
68 }
69 
flash_set_dummy_out(void)70 void flash_set_dummy_out(void)
71 {
72 	REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
73 	REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
74 }
75 
flash_dummy_config(const esp_image_header_t * pfhdr)76 void flash_dummy_config(const esp_image_header_t *pfhdr)
77 {
78 	configure_spi_pins(1);
79 	flash_set_dummy_out();
80 }
81 
flash_cs_timing_config(void)82 void flash_cs_timing_config(void)
83 {
84 	/* SPI0/1 share the cs_hold / cs_setup, cd_hold_time / cd_setup_time, cs_hold_delay
85 	 * registers for FLASH, so we only need to set SPI0 related registers here
86 	 */
87 	if (flash_is_octal_mode_enabled()) {
88 
89 		SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
90 		SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, FLASH_CS_HOLD_TIME,
91 				  SPI_MEM_CS_HOLD_TIME_S);
92 		SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V,
93 				  FLASH_CS_SETUP_TIME, SPI_MEM_CS_SETUP_TIME_S);
94 		/* CS high time */
95 		SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_DELAY_V,
96 				  FLASH_CS_HOLD_DELAY, SPI_MEM_CS_HOLD_DELAY_S);
97 	} else {
98 		SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0,
99 				  SPI_MEM_CS_HOLD_TIME_S);
100 		SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0,
101 				  SPI_MEM_CS_SETUP_TIME_S);
102 		SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
103 	}
104 }
105 
init_flash_configure(void)106 static void init_flash_configure(void)
107 {
108 	flash_dummy_config(&bootloader_image_hdr);
109 	flash_cs_timing_config();
110 }
111 
print_flash_info(const esp_image_header_t * bootloader_hdr)112 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
113 {
114 	ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
115 	ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
116 	ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
117 	ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
118 	ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
119 
120 	const char *str;
121 
122 	switch (bootloader_hdr->spi_speed) {
123 	case ESP_IMAGE_SPI_SPEED_DIV_2:
124 		str = "40MHz";
125 		break;
126 	case ESP_IMAGE_SPI_SPEED_DIV_3:
127 		str = "26.7MHz";
128 		break;
129 	case ESP_IMAGE_SPI_SPEED_DIV_4:
130 		str = "20MHz";
131 		break;
132 	case ESP_IMAGE_SPI_SPEED_DIV_1:
133 		str = "80MHz";
134 		break;
135 	default:
136 		str = "20MHz";
137 		break;
138 	}
139 	ESP_EARLY_LOGI(TAG, "Boot SPI Speed : %s", str);
140 
141 	/* SPI mode could have been set to QIO during boot already,
142 	 * so test the SPI registers not the flash header
143 	 */
144 	uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
145 
146 	if (spi_ctrl & SPI_MEM_FREAD_QIO) {
147 		str = "QIO";
148 	} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
149 		str = "QOUT";
150 	} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
151 		str = "DIO";
152 	} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
153 		str = "DOUT";
154 	} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
155 		str = "FAST READ";
156 	} else {
157 		str = "SLOW READ";
158 	}
159 	ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
160 
161 	switch (bootloader_hdr->spi_size) {
162 	case ESP_IMAGE_FLASH_SIZE_1MB:
163 		str = "1MB";
164 		break;
165 	case ESP_IMAGE_FLASH_SIZE_2MB:
166 		str = "2MB";
167 		break;
168 	case ESP_IMAGE_FLASH_SIZE_4MB:
169 		str = "4MB";
170 		break;
171 	case ESP_IMAGE_FLASH_SIZE_8MB:
172 		str = "8MB";
173 		break;
174 	case ESP_IMAGE_FLASH_SIZE_16MB:
175 		str = "16MB";
176 		break;
177 	case ESP_IMAGE_FLASH_SIZE_32MB:
178 		str = "32MB";
179 		break;
180 	case ESP_IMAGE_FLASH_SIZE_64MB:
181 		str = "64MB";
182 		break;
183 	case ESP_IMAGE_FLASH_SIZE_128MB:
184 		str = "128MB";
185 		break;
186 	default:
187 		str = "2MB";
188 		break;
189 	}
190 	ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
191 }
192 
update_flash_config(const esp_image_header_t * bootloader_hdr)193 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
194 {
195 	volatile uint32_t size;
196 
197 	switch (bootloader_hdr->spi_size) {
198 	case ESP_IMAGE_FLASH_SIZE_1MB:
199 		size = 1;
200 		break;
201 	case ESP_IMAGE_FLASH_SIZE_2MB:
202 		size = 2;
203 		break;
204 	case ESP_IMAGE_FLASH_SIZE_4MB:
205 		size = 4;
206 		break;
207 	case ESP_IMAGE_FLASH_SIZE_8MB:
208 		size = 8;
209 		break;
210 	case ESP_IMAGE_FLASH_SIZE_16MB:
211 		size = 16;
212 		break;
213 	case ESP_IMAGE_FLASH_SIZE_32MB:
214 		size = 32;
215 		break;
216 	case ESP_IMAGE_FLASH_SIZE_64MB:
217 		size = 64;
218 		break;
219 	case ESP_IMAGE_FLASH_SIZE_128MB:
220 		size = 128;
221 		break;
222 	default:
223 		size = 2;
224 	}
225 
226 	cache_hal_disable(CACHE_TYPE_ALL);
227 	/* Set flash chip size */
228 	esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000,
229 				      0x100, 0xffff);
230 	cache_hal_enable(CACHE_TYPE_ALL);
231 }
232 
init_spi_flash(void)233 int init_spi_flash(void)
234 {
235 	init_flash_configure();
236 #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
237 	const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
238 
239 	if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI &&
240 	    spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
241 		ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable "
242 				    "CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
243 		return ESP_FAIL;
244 	}
245 #endif
246 
247 #if CONFIG_SPI_FLASH_HPM_ENABLE
248 	/* Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot. */
249 	bootloader_spi_flash_reset();
250 #endif
251 
252 	bootloader_flash_unlock();
253 
254 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
255 	if (!flash_is_octal_mode_enabled()) {
256 		bootloader_enable_qio_mode();
257 	}
258 #endif
259 
260 	print_flash_info(&bootloader_image_hdr);
261 	update_flash_config(&bootloader_image_hdr);
262 	/* ensure the flash is write-protected */
263 	bootloader_enable_wp();
264 	return ESP_OK;
265 }
266 
flash_update_id(void)267 void flash_update_id(void)
268 {
269 	esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
270 
271 	chip->device_id = bootloader_read_flash_id();
272 }
273