1 /*
2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "soc_flash_init.h"
7 #include <stdbool.h>
8 #include <string.h>
9
10 #include "esp_err.h"
11 #include "esp_log.h"
12 #include "esp_rom_gpio.h"
13 #include "esp_rom_efuse.h"
14 #include "esp32c3/rom/gpio.h"
15 #include "esp32c3/rom/spi_flash.h"
16 #include "esp32c3/rom/efuse.h"
17 #include "soc/gpio_periph.h"
18 #include "soc/efuse_reg.h"
19 #include "soc/spi_reg.h"
20 #include "soc/spi_mem_reg.h"
21 #include "soc/soc_caps.h"
22 #include "flash_qio_mode.h"
23 #include "bootloader_flash_config.h"
24 #include "bootloader_common.h"
25 #include "bootloader_flash_priv.h"
26 #include "bootloader_init.h"
27 #include "hal/mmu_hal.h"
28 #include "hal/cache_hal.h"
29 #include "hal/mmu_ll.h"
30
31 #define FLASH_IO_MATRIX_DUMMY_40M 0
32 #define FLASH_IO_MATRIX_DUMMY_80M 0
33
34 #define TAG "flash_init"
35
36 extern esp_image_header_t bootloader_image_hdr;
37
flash_update_id(void)38 void flash_update_id(void)
39 {
40 esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
41
42 chip->device_id = bootloader_read_flash_id();
43 }
44
flash_cs_timing_config(void)45 void flash_cs_timing_config(void)
46 {
47 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
48 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
49 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0,
50 SPI_MEM_CS_SETUP_TIME_S);
51 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
52 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
53 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0,
54 SPI_MEM_CS_SETUP_TIME_S);
55 }
56
flash_clock_config(const esp_image_header_t * pfhdr)57 void flash_clock_config(const esp_image_header_t *pfhdr)
58 {
59 uint32_t spi_clk_div = 0;
60
61 switch (pfhdr->spi_speed) {
62 case ESP_IMAGE_SPI_SPEED_DIV_1:
63 spi_clk_div = 1;
64 break;
65 case ESP_IMAGE_SPI_SPEED_DIV_2:
66 spi_clk_div = 2;
67 break;
68 case ESP_IMAGE_SPI_SPEED_DIV_3:
69 spi_clk_div = 3;
70 break;
71 case ESP_IMAGE_SPI_SPEED_DIV_4:
72 spi_clk_div = 4;
73 break;
74 default:
75 break;
76 }
77 esp_rom_spiflash_config_clk(spi_clk_div, 0);
78 }
79
flash_set_dummy_out(void)80 void flash_set_dummy_out(void)
81 {
82 REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
83 REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
84 }
85
configure_spi_pins(int drv)86 void configure_spi_pins(int drv)
87 {
88 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
89 uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
90 uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
91 uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
92 uint8_t d_gpio_num = SPI_D_GPIO_NUM;
93 uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
94 uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
95 uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
96
97 if (spiconfig == 0) {
98
99 } else {
100 clk_gpio_num = spiconfig & 0x3f;
101 q_gpio_num = (spiconfig >> 6) & 0x3f;
102 d_gpio_num = (spiconfig >> 12) & 0x3f;
103 cs0_gpio_num = (spiconfig >> 18) & 0x3f;
104 hd_gpio_num = (spiconfig >> 24) & 0x3f;
105 wp_gpio_num = wp_pin;
106 }
107 esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
108 esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
109 esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
110 esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
111 if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
112 esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
113 }
114 if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
115 esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
116 }
117 }
118
flash_dummy_config(const esp_image_header_t * pfhdr)119 void flash_dummy_config(const esp_image_header_t *pfhdr)
120 {
121 configure_spi_pins(1);
122 flash_set_dummy_out();
123 }
124
update_flash_config(const esp_image_header_t * bootloader_hdr)125 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
126 {
127 volatile uint32_t size;
128
129 switch (bootloader_hdr->spi_size) {
130 case ESP_IMAGE_FLASH_SIZE_1MB:
131 size = 1;
132 break;
133 case ESP_IMAGE_FLASH_SIZE_2MB:
134 size = 2;
135 break;
136 case ESP_IMAGE_FLASH_SIZE_4MB:
137 size = 4;
138 break;
139 case ESP_IMAGE_FLASH_SIZE_8MB:
140 size = 8;
141 break;
142 case ESP_IMAGE_FLASH_SIZE_16MB:
143 size = 16;
144 break;
145 default:
146 size = 2;
147 }
148 cache_hal_disable(CACHE_TYPE_ALL);
149 /* Set flash chip size */
150 esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000,
151 0x10000, 0x1000, 0x100, 0xffff);
152 cache_hal_enable(CACHE_TYPE_ALL);
153 }
154
print_flash_info(const esp_image_header_t * bootloader_hdr)155 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
156 {
157 ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
158 ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
159 ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
160 ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
161 ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
162
163 const char *str;
164
165 switch (bootloader_hdr->spi_speed) {
166 case ESP_IMAGE_SPI_SPEED_DIV_2:
167 str = "40MHz";
168 break;
169 case ESP_IMAGE_SPI_SPEED_DIV_3:
170 str = "26.7MHz";
171 break;
172 case ESP_IMAGE_SPI_SPEED_DIV_4:
173 str = "20MHz";
174 break;
175 case ESP_IMAGE_SPI_SPEED_DIV_1:
176 str = "80MHz";
177 break;
178 default:
179 str = "20MHz";
180 break;
181 }
182 ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str);
183
184 /* SPI mode could have been set to QIO during boot already,
185 * so test the SPI registers not the flash header
186 */
187 uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
188
189 if (spi_ctrl & SPI_MEM_FREAD_QIO) {
190 str = "QIO";
191 } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
192 str = "QOUT";
193 } else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
194 str = "DIO";
195 } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
196 str = "DOUT";
197 } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
198 str = "FAST READ";
199 } else {
200 str = "SLOW READ";
201 }
202 ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
203
204 switch (bootloader_hdr->spi_size) {
205 case ESP_IMAGE_FLASH_SIZE_1MB:
206 str = "1MB";
207 break;
208 case ESP_IMAGE_FLASH_SIZE_2MB:
209 str = "2MB";
210 break;
211 case ESP_IMAGE_FLASH_SIZE_4MB:
212 str = "4MB";
213 break;
214 case ESP_IMAGE_FLASH_SIZE_8MB:
215 str = "8MB";
216 break;
217 case ESP_IMAGE_FLASH_SIZE_16MB:
218 str = "16MB";
219 break;
220 default:
221 str = "2MB";
222 break;
223 }
224 ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
225 }
226
init_flash_configure(void)227 static void init_flash_configure(void)
228 {
229 flash_dummy_config(&bootloader_image_hdr);
230 flash_cs_timing_config();
231 }
232
spi_flash_resume(void)233 static void spi_flash_resume(void)
234 {
235 bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
236 esp_rom_spiflash_wait_idle(&g_rom_flashchip);
237 }
238
init_spi_flash(void)239 int init_spi_flash(void)
240 {
241 init_flash_configure();
242 #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
243 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
244
245 if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI &&
246 spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
247 ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable "
248 "CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
249 return ESP_FAIL;
250 }
251 #endif
252
253 spi_flash_resume();
254 bootloader_flash_unlock();
255
256 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
257 bootloader_enable_qio_mode();
258 #endif
259
260 print_flash_info(&bootloader_image_hdr);
261 update_flash_config(&bootloader_image_hdr);
262 /* ensure the flash is write-protected */
263 bootloader_enable_wp();
264 return ESP_OK;
265 }
266
