1 /*
2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stdbool.h>
7 #include <assert.h>
8 #include <string.h>
9 #include "esp_err.h"
10 #include "esp_log.h"
11 #include "esp_rom_gpio.h"
12 #include "esp_rom_efuse.h"
13 #include "esp32c6/rom/gpio.h"
14 #include "esp32c6/rom/spi_flash.h"
15 #include "esp32c6/rom/efuse.h"
16 #include "soc/gpio_periph.h"
17 #include "soc/efuse_reg.h"
18 #include "soc/spi_reg.h"
19 #include "soc/spi_mem_reg.h"
20 #include "soc/soc_caps.h"
21 #include "flash_qio_mode.h"
22 #include "bootloader_flash_config.h"
23 #include "bootloader_common.h"
24 #include "bootloader_flash_priv.h"
25 #include "bootloader_init.h"
26 #include "hal/mmu_hal.h"
27 #include "hal/cache_hal.h"
28 #include "hal/mmu_ll.h"
29
30 #define TAG "flash_init"
31
32 extern esp_image_header_t bootloader_image_hdr;
33
flash_update_id(void)34 void flash_update_id(void)
35 {
36 esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
37
38 chip->device_id = bootloader_read_flash_id();
39 }
40
flash_cs_timing_config(void)41 void flash_cs_timing_config(void)
42 {
43 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
44 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
45 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0,
46 SPI_MEM_CS_SETUP_TIME_S);
47 }
48
flash_clock_config(const esp_image_header_t * pfhdr)49 void flash_clock_config(const esp_image_header_t *pfhdr)
50 {
51 uint32_t spi_clk_div = 0;
52
53 switch (pfhdr->spi_speed) {
54 case ESP_IMAGE_SPI_SPEED_DIV_1:
55 spi_clk_div = 1;
56 break;
57 case ESP_IMAGE_SPI_SPEED_DIV_2:
58 spi_clk_div = 2;
59 break;
60 case ESP_IMAGE_SPI_SPEED_DIV_3:
61 spi_clk_div = 3;
62 break;
63 case ESP_IMAGE_SPI_SPEED_DIV_4:
64 spi_clk_div = 4;
65 break;
66 default:
67 break;
68 }
69 esp_rom_spiflash_config_clk(spi_clk_div, 0);
70 }
71
configure_spi_pins(int drv)72 void configure_spi_pins(int drv)
73 {
74 uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
75 uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
76 uint8_t d_gpio_num = SPI_D_GPIO_NUM;
77 uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
78 uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
79 uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
80
81 esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
82 esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
83 esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
84 esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
85 esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
86 esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
87 }
88
update_flash_config(const esp_image_header_t * bootloader_hdr)89 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
90 {
91 volatile uint32_t size;
92
93 switch (bootloader_hdr->spi_size) {
94 case ESP_IMAGE_FLASH_SIZE_1MB:
95 size = 1;
96 break;
97 case ESP_IMAGE_FLASH_SIZE_2MB:
98 size = 2;
99 break;
100 case ESP_IMAGE_FLASH_SIZE_4MB:
101 size = 4;
102 break;
103 case ESP_IMAGE_FLASH_SIZE_8MB:
104 size = 8;
105 break;
106 case ESP_IMAGE_FLASH_SIZE_16MB:
107 size = 16;
108 break;
109 default:
110 size = 2;
111 }
112 cache_hal_disable(CACHE_TYPE_ALL);
113 /* Set flash chip size */
114 esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000,
115 0x10000, 0x1000, 0x100, 0xffff);
116 cache_hal_enable(CACHE_TYPE_ALL);
117 }
118
print_flash_info(const esp_image_header_t * bootloader_hdr)119 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
120 {
121 ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
122 ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
123 ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
124 ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
125 ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
126
127 const char *str;
128
129 switch (bootloader_hdr->spi_speed) {
130 case ESP_IMAGE_SPI_SPEED_DIV_2:
131 str = "40MHz";
132 break;
133 case ESP_IMAGE_SPI_SPEED_DIV_3:
134 str = "26.7MHz";
135 break;
136 case ESP_IMAGE_SPI_SPEED_DIV_4:
137 str = "20MHz";
138 break;
139 case ESP_IMAGE_SPI_SPEED_DIV_1:
140 str = "80MHz";
141 break;
142 default:
143 str = "20MHz";
144 break;
145 }
146 ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str);
147
148 /* SPI mode could have been set to QIO during boot already,
149 * so test the SPI registers not the flash header
150 */
151 uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
152
153 if (spi_ctrl & SPI_MEM_FREAD_QIO) {
154 str = "QIO";
155 } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
156 str = "QOUT";
157 } else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
158 str = "DIO";
159 } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
160 str = "DOUT";
161 } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
162 str = "FAST READ";
163 } else {
164 str = "SLOW READ";
165 }
166 ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
167
168 switch (bootloader_hdr->spi_size) {
169 case ESP_IMAGE_FLASH_SIZE_1MB:
170 str = "1MB";
171 break;
172 case ESP_IMAGE_FLASH_SIZE_2MB:
173 str = "2MB";
174 break;
175 case ESP_IMAGE_FLASH_SIZE_4MB:
176 str = "4MB";
177 break;
178 case ESP_IMAGE_FLASH_SIZE_8MB:
179 str = "8MB";
180 break;
181 case ESP_IMAGE_FLASH_SIZE_16MB:
182 str = "16MB";
183 break;
184 default:
185 str = "2MB";
186 break;
187 }
188 ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
189 }
190
init_flash_configure(void)191 static void init_flash_configure(void)
192 {
193 configure_spi_pins(1);
194 flash_cs_timing_config();
195 }
196
spi_flash_resume(void)197 static void spi_flash_resume(void)
198 {
199 bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
200 esp_rom_spiflash_wait_idle(&g_rom_flashchip);
201 }
202
init_spi_flash(void)203 esp_err_t init_spi_flash(void)
204 {
205 init_flash_configure();
206 spi_flash_resume();
207 bootloader_flash_unlock();
208
209 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
210 bootloader_enable_qio_mode();
211 #endif
212
213 #if CONFIG_ESPTOOLPY_FLASHFREQ_80M
214 bootloader_image_hdr.spi_speed = ESP_IMAGE_SPI_SPEED_DIV_1;
215 #endif
216 print_flash_info(&bootloader_image_hdr);
217 update_flash_config(&bootloader_image_hdr);
218 /* ensure the flash is write-protected */
219 bootloader_enable_wp();
220 return ESP_OK;
221 }
222
