1 /*
2  * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include "soc_flash_init.h"
8 
9 #include <stdbool.h>
10 #include <string.h>
11 
12 #include "esp_err.h"
13 #include "esp_log.h"
14 #include "esp_rom_gpio.h"
15 #include "esp32c2/rom/gpio.h"
16 #include "esp32c2/rom/spi_flash.h"
17 #include "soc/gpio_periph.h"
18 #include "soc/efuse_reg.h"
19 #include "soc/spi_reg.h"
20 #include "soc/spi_mem_reg.h"
21 #include "soc/soc_caps.h"
22 #include "flash_qio_mode.h"
23 #include "bootloader_flash_priv.h"
24 #include "bootloader_init.h"
25 #include "hal/mmu_hal.h"
26 #include "hal/cache_hal.h"
27 #include "hal/mmu_ll.h"
28 
29 #define FLASH_IO_MATRIX_DUMMY_40M 0
30 #define FLASH_IO_MATRIX_DUMMY_80M 0
31 
32 #define TAG "soc_flash_init"
33 
34 extern esp_image_header_t bootloader_image_hdr;
35 
flash_update_id(void)36 void flash_update_id(void)
37 {
38 	esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
39 
40 	chip->device_id = bootloader_read_flash_id();
41 }
42 
flash_cs_timing_config(void)43 void flash_cs_timing_config(void)
44 {
45 	SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
46 	SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
47 	SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0,
48 			  SPI_MEM_CS_SETUP_TIME_S);
49 }
50 
flash_clock_config(const esp_image_header_t * pfhdr)51 void flash_clock_config(const esp_image_header_t *pfhdr)
52 {
53 	uint32_t spi_clk_div = 0;
54 
55 	switch (pfhdr->spi_speed) {
56 	case ESP_IMAGE_SPI_SPEED_DIV_1:
57 		spi_clk_div = 1;
58 		break;
59 	case ESP_IMAGE_SPI_SPEED_DIV_2:
60 		spi_clk_div = 2;
61 		break;
62 	case ESP_IMAGE_SPI_SPEED_DIV_3:
63 		spi_clk_div = 3;
64 		break;
65 	case ESP_IMAGE_SPI_SPEED_DIV_4:
66 		spi_clk_div = 4;
67 		break;
68 	default:
69 		break;
70 	}
71 	esp_rom_spiflash_config_clk(spi_clk_div, 0);
72 }
73 
flash_set_dummy_out(void)74 void flash_set_dummy_out(void)
75 {
76 	REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
77 	REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
78 }
79 
configure_spi_pins(int drv)80 void configure_spi_pins(int drv)
81 {
82 	uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
83 	uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
84 	uint8_t d_gpio_num = SPI_D_GPIO_NUM;
85 	uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
86 	uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
87 	uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
88 
89 	esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
90 	esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
91 	esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
92 	esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
93 	if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
94 		esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
95 	}
96 	if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
97 		esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
98 	}
99 }
100 
flash_dummy_config(const esp_image_header_t * pfhdr)101 void flash_dummy_config(const esp_image_header_t *pfhdr)
102 {
103 	configure_spi_pins(1);
104 	flash_set_dummy_out();
105 }
106 
update_flash_config(const esp_image_header_t * bootloader_hdr)107 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
108 {
109 	volatile uint32_t size;
110 
111 	switch (bootloader_hdr->spi_size) {
112 	case ESP_IMAGE_FLASH_SIZE_1MB:
113 		size = 1;
114 		break;
115 	case ESP_IMAGE_FLASH_SIZE_2MB:
116 		size = 2;
117 		break;
118 	case ESP_IMAGE_FLASH_SIZE_4MB:
119 		size = 4;
120 		break;
121 	case ESP_IMAGE_FLASH_SIZE_8MB:
122 		size = 8;
123 		break;
124 	case ESP_IMAGE_FLASH_SIZE_16MB:
125 		size = 16;
126 		break;
127 	default:
128 		size = 2;
129 	}
130 	cache_hal_disable(CACHE_TYPE_ALL);
131 	/* Set flash chip size */
132 	esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000,
133 				      0x10000, 0x1000, 0x100, 0xffff);
134 	cache_hal_enable(CACHE_TYPE_ALL);
135 }
136 
print_flash_info(const esp_image_header_t * bootloader_hdr)137 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
138 {
139 	ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
140 	ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
141 	ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
142 	ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
143 	ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
144 
145 	const char *str;
146 
147 	switch (bootloader_hdr->spi_speed) {
148 	case ESP_IMAGE_SPI_SPEED_DIV_2:
149 		str = "30MHz";
150 		break;
151 	case ESP_IMAGE_SPI_SPEED_DIV_3:
152 		str = "20MHz";
153 		break;
154 	case ESP_IMAGE_SPI_SPEED_DIV_4:
155 		str = "15MHz";
156 		break;
157 	case ESP_IMAGE_SPI_SPEED_DIV_1:
158 		str = "60MHz";
159 		break;
160 	default:
161 		str = "15MHz";
162 		break;
163 	}
164 	ESP_EARLY_LOGI(TAG, "SPI Speed      : %s", str);
165 
166 	/* SPI mode could have been set to QIO during boot already,
167 	 * so test the SPI registers not the flash header
168 	 */
169 	uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
170 
171 	if (spi_ctrl & SPI_MEM_FREAD_QIO) {
172 		str = "QIO";
173 	} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
174 		str = "QOUT";
175 	} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
176 		str = "DIO";
177 	} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
178 		str = "DOUT";
179 	} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
180 		str = "FAST READ";
181 	} else {
182 		str = "SLOW READ";
183 	}
184 	ESP_EARLY_LOGI(TAG, "SPI Mode       : %s", str);
185 
186 	switch (bootloader_hdr->spi_size) {
187 	case ESP_IMAGE_FLASH_SIZE_1MB:
188 		str = "1MB";
189 		break;
190 	case ESP_IMAGE_FLASH_SIZE_2MB:
191 		str = "2MB";
192 		break;
193 	case ESP_IMAGE_FLASH_SIZE_4MB:
194 		str = "4MB";
195 		break;
196 	case ESP_IMAGE_FLASH_SIZE_8MB:
197 		str = "8MB";
198 		break;
199 	case ESP_IMAGE_FLASH_SIZE_16MB:
200 		str = "16MB";
201 		break;
202 	default:
203 		str = "2MB";
204 		break;
205 	}
206 	ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
207 }
208 
print_mmu_page_size(void)209 static void print_mmu_page_size(void)
210 {
211 	mmu_page_size_t page_size = mmu_ll_get_page_size(0);
212 
213 	int size = (page_size == MMU_PAGE_16KB   ? 16
214 		    : page_size == MMU_PAGE_32KB ? 32
215 		    : page_size == MMU_PAGE_64KB ? 64
216 						 : 0);
217 
218 	ESP_EARLY_LOGI(TAG, "MMU Page Size  : %dK", size);
219 }
220 
init_flash_configure(void)221 static void init_flash_configure(void)
222 {
223 	flash_dummy_config(&bootloader_image_hdr);
224 	flash_cs_timing_config();
225 }
226 
spi_flash_resume(void)227 static void spi_flash_resume(void)
228 {
229 	bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
230 	esp_rom_spiflash_wait_idle(&g_rom_flashchip);
231 }
232 
init_spi_flash(void)233 esp_err_t init_spi_flash(void)
234 {
235 	init_flash_configure();
236 
237 	spi_flash_resume();
238 	bootloader_flash_unlock();
239 
240 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
241 	bootloader_enable_qio_mode();
242 #endif
243 
244 	print_mmu_page_size();
245 	print_flash_info(&bootloader_image_hdr);
246 	update_flash_config(&bootloader_image_hdr);
247 	/* ensure the flash is write-protected */
248 	bootloader_enable_wp();
249 	return ESP_OK;
250 }
251