1 /*
2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdbool.h>
8 #include <assert.h>
9 #include <string.h>
10
11 #include "flash_init.h"
12
13 #include "esp_err.h"
14 #include "esp_log.h"
15 #include "esp_rom_gpio.h"
16 #include "esp_rom_efuse.h"
17 #include "esp32s2/rom/spi_flash.h"
18 #include "soc/efuse_reg.h"
19 #include "soc/io_mux_reg.h"
20 #include "soc/spi_reg.h"
21 #include "soc/spi_mem_reg.h"
22 #include "soc/soc_caps.h"
23 #include "flash_qio_mode.h"
24 #include "bootloader_flash_config.h"
25 #include "bootloader_flash_priv.h"
26 #include "bootloader_common.h"
27 #include "hal/mmu_hal.h"
28 #include "hal/cache_hal.h"
29
30 #define TAG "flash_init"
31
32 extern esp_image_header_t bootloader_image_hdr;
33
34 #define FLASH_IO_MATRIX_DUMMY_40M 0
35 #define FLASH_IO_MATRIX_DUMMY_80M 0
36
37 #define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3
38
configure_spi_pins(int drv)39 void configure_spi_pins(int drv)
40 {
41 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
42 uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
43 uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
44 uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
45 uint8_t d_gpio_num = SPI_D_GPIO_NUM;
46 uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
47 uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
48 uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
49
50 if (spiconfig == 0) {
51
52 } else {
53 clk_gpio_num = spiconfig & 0x3f;
54 q_gpio_num = (spiconfig >> 6) & 0x3f;
55 d_gpio_num = (spiconfig >> 12) & 0x3f;
56 cs0_gpio_num = (spiconfig >> 18) & 0x3f;
57 hd_gpio_num = (spiconfig >> 24) & 0x3f;
58 wp_gpio_num = wp_pin;
59 }
60 esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
61 esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
62 esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
63 esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
64 if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
65 esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
66 }
67 if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
68 esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
69 }
70 }
71
flash_set_dummy_out(void)72 void flash_set_dummy_out(void)
73 {
74 REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
75 REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
76 }
77
flash_dummy_config(const esp_image_header_t * pfhdr)78 void flash_dummy_config(const esp_image_header_t *pfhdr)
79 {
80 configure_spi_pins(1);
81 flash_set_dummy_out();
82 }
83
flash_cs_timing_config(void)84 void flash_cs_timing_config(void)
85 {
86 SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
87 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
88 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0,
89 SPI_MEM_CS_SETUP_TIME_S);
90 SET_PERI_REG_MASK(SPI_MEM_USER_REG(1), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
91 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_HOLD_TIME_V, 1, SPI_MEM_CS_HOLD_TIME_S);
92 SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(1), SPI_MEM_CS_SETUP_TIME_V, 0,
93 SPI_MEM_CS_SETUP_TIME_S);
94 }
95
init_flash_configure(void)96 static void init_flash_configure(void)
97 {
98 flash_dummy_config(&bootloader_image_hdr);
99 flash_cs_timing_config();
100 }
101
print_flash_info(const esp_image_header_t * bootloader_hdr)102 static void print_flash_info(const esp_image_header_t *bootloader_hdr)
103 {
104 ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
105 ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
106 ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
107 ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
108 ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
109
110 const char *str;
111
112 switch (bootloader_hdr->spi_speed) {
113 case ESP_IMAGE_SPI_SPEED_DIV_2:
114 str = "40MHz";
115 break;
116 case ESP_IMAGE_SPI_SPEED_DIV_3:
117 str = "26.7MHz";
118 break;
119 case ESP_IMAGE_SPI_SPEED_DIV_4:
120 str = "20MHz";
121 break;
122 case ESP_IMAGE_SPI_SPEED_DIV_1:
123 str = "80MHz";
124 break;
125 default:
126 str = "20MHz";
127 break;
128 }
129 ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str);
130
131 /* SPI mode could have been set to QIO during boot already,
132 * so test the SPI registers not the flash header
133 */
134 uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
135
136 if (spi_ctrl & SPI_MEM_FREAD_QIO) {
137 str = "QIO";
138 } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
139 str = "QOUT";
140 } else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
141 str = "DIO";
142 } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
143 str = "DOUT";
144 } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
145 str = "FAST READ";
146 } else {
147 str = "SLOW READ";
148 }
149 ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str);
150
151 switch (bootloader_hdr->spi_size) {
152 case ESP_IMAGE_FLASH_SIZE_1MB:
153 str = "1MB";
154 break;
155 case ESP_IMAGE_FLASH_SIZE_2MB:
156 str = "2MB";
157 break;
158 case ESP_IMAGE_FLASH_SIZE_4MB:
159 str = "4MB";
160 break;
161 case ESP_IMAGE_FLASH_SIZE_8MB:
162 str = "8MB";
163 break;
164 case ESP_IMAGE_FLASH_SIZE_16MB:
165 str = "16MB";
166 break;
167 case ESP_IMAGE_FLASH_SIZE_32MB:
168 str = "32MB";
169 break;
170 case ESP_IMAGE_FLASH_SIZE_64MB:
171 str = "64MB";
172 break;
173 case ESP_IMAGE_FLASH_SIZE_128MB:
174 str = "128MB";
175 break;
176 default:
177 str = "2MB";
178 break;
179 }
180 ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str);
181 }
182
update_flash_config(const esp_image_header_t * bootloader_hdr)183 static void update_flash_config(const esp_image_header_t *bootloader_hdr)
184 {
185 volatile uint32_t size;
186
187 switch (bootloader_hdr->spi_size) {
188 case ESP_IMAGE_FLASH_SIZE_1MB:
189 size = 1;
190 break;
191 case ESP_IMAGE_FLASH_SIZE_2MB:
192 size = 2;
193 break;
194 case ESP_IMAGE_FLASH_SIZE_4MB:
195 size = 4;
196 break;
197 case ESP_IMAGE_FLASH_SIZE_8MB:
198 size = 8;
199 break;
200 case ESP_IMAGE_FLASH_SIZE_16MB:
201 size = 16;
202 break;
203 case ESP_IMAGE_FLASH_SIZE_32MB:
204 size = 32;
205 break;
206 case ESP_IMAGE_FLASH_SIZE_64MB:
207 size = 64;
208 break;
209 case ESP_IMAGE_FLASH_SIZE_128MB:
210 size = 128;
211 break;
212 default:
213 size = 2;
214 }
215 cache_hal_disable(CACHE_TYPE_ALL);
216 /* Set flash chip size */
217 esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000,
218 0x100, 0xffff);
219 cache_hal_enable(CACHE_TYPE_ALL);
220 }
221
init_spi_flash(void)222 esp_err_t init_spi_flash(void)
223 {
224 init_flash_configure();
225 #ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
226 const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
227
228 if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI &&
229 spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
230 ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable "
231 "CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
232 return ESP_FAIL;
233 }
234 #endif
235
236 bootloader_flash_unlock();
237
238 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
239 bootloader_enable_qio_mode();
240 #endif
241
242 print_flash_info(&bootloader_image_hdr);
243 update_flash_config(&bootloader_image_hdr);
244 /* ensure the flash is write-protected */
245 bootloader_enable_wp();
246 return ESP_OK;
247 }
248
flash_update_id(void)249 void flash_update_id(void)
250 {
251 g_rom_flashchip.device_id = bootloader_read_flash_id();
252 }
253
flash_update_size(uint32_t size)254 void flash_update_size(uint32_t size)
255 {
256 g_rom_flashchip.chip_size = size;
257 }
258
flash_clock_config(const esp_image_header_t * pfhdr)259 void flash_clock_config(const esp_image_header_t *pfhdr)
260 {
261 uint32_t spi_clk_div = 0;
262
263 switch (pfhdr->spi_speed) {
264 case ESP_IMAGE_SPI_SPEED_DIV_1:
265 spi_clk_div = 1;
266 break;
267 case ESP_IMAGE_SPI_SPEED_DIV_2:
268 spi_clk_div = 2;
269 break;
270 case ESP_IMAGE_SPI_SPEED_DIV_3:
271 spi_clk_div = 3;
272 break;
273 case ESP_IMAGE_SPI_SPEED_DIV_4:
274 spi_clk_div = 4;
275 break;
276 default:
277 break;
278 }
279 esp_rom_spiflash_config_clk(spi_clk_div, 0);
280 esp_rom_spiflash_config_clk(spi_clk_div, 1);
281 }
282
