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Searched refs:pllr (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32g4.c68 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32g0_u0.c64 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32l4_l5_wb_wl.c83 pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
Dclock_stm32_ll_common.h28 #define pllr(v) z_pllr(v) macro
Dclock_stm32f2_f4_f7.c100 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR)); in config_pll_sysclock()
/Zephyr-latest/boards/renesas/mck_ra8t1/
Dmck_ra8t1.dts74 pllr {
/Zephyr-latest/dts/arm/renesas/ra/ra8/
Dr7fa8t1xh.dtsi70 pllr: pllr { label
Dr7fa8m1xh.dtsi72 pllr: pllr { label
Dr7fa8d1xh.dtsi102 pllr: pllr { label
/Zephyr-latest/boards/renesas/ek_ra8d1/
Dek_ra8d1.dts109 pllr {
/Zephyr-latest/boards/renesas/ek_ra8m1/
Dek_ra8m1.dts146 pllr {