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/Zephyr-latest/tests/drivers/clock_control/adsp_clock/src/
Dmain.c10 static void check_clocks(struct adsp_cpu_clock_info *clocks, uint32_t freq_idx) in check_clocks() argument
16 zassert_equal(clocks[i].current_freq, freq_idx, ""); in check_clocks()
22 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
24 zassert_not_null(clocks, ""); in ZTEST()
27 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO); in ZTEST()
30 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_HPRO); in ZTEST()
34 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_WOVCRO); in ZTEST()
40 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
43 zassert_not_null(clocks, ""); in ZTEST()
47 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO); in ZTEST()
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
24 atmel,assigned-clocks = <&gclk 0>;
36 clocks = <&gclk 25>, <&mclk 0x1c 6>;
38 atmel,assigned-clocks = <&gclk 0>;
50 clocks = <&gclk 26>, <&mclk 0x1c 7>;
52 atmel,assigned-clocks = <&gclk 0>;
64 clocks = <&gclk 32>, <&mclk 0x1c 12>;
66 atmel,assigned-clocks = <&gclk 0>;
72 clocks = <&gclk 18>, <&mclk 0x1c 0>;
74 atmel,assigned-clocks = <&gclk 0>;
[all …]
Dsamd20.dtsi22 clocks = <&gclk 0x13>, <&pm 0x20 8>;
24 atmel,assigned-clocks = <&gclk 0>;
33 clocks = <&gclk 0x14>, <&pm 0x20 10>;
35 atmel,assigned-clocks = <&gclk 0>;
44 clocks = <&gclk 0x16>, <&pm 0x20 14>;
46 atmel,assigned-clocks = <&gclk 0>;
55 clocks = <&gclk 26>, <&pm 0x20 18>;
57 atmel,assigned-clocks = <&gclk 0>;
62 clocks = <&gclk 2>, <&pm 0x18 5>;
64 atmel,assigned-clocks = <&gclk 4>;
[all …]
Dsamd21.dtsi42 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
44 atmel,assigned-clocks = <&gclk 0>;
53 clocks = <&gclk 26>, <&pm 0x20 8>;
55 atmel,assigned-clocks = <&gclk 0>;
67 clocks = <&gclk 26>, <&pm 0x20 9>;
69 atmel,assigned-clocks = <&gclk 0>;
81 clocks = <&gclk 27>, <&pm 0x20 10>;
83 atmel,assigned-clocks = <&gclk 0>;
95 clocks = <&gclk 33>, <&pm 0x20 18>;
97 atmel,assigned-clocks = <&gclk 0>;
[all …]
Dsamx7x.dtsi53 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
63 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
73 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>,
90 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>,
107 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>,
125 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
136 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
144 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
155 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
163 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
[all …]
Dsam4e.dtsi64 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
73 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
82 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
100 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
109 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
120 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
132 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
148 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
156 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
[all …]
Dsamc21.dtsi24 clocks = <&gclk 34>, <&mclk 0x1c 18>;
26 atmel,assigned-clocks = <&gclk 0>;
39 clocks = <&gclk 23>, <&mclk 0x1c 5>;
41 atmel,assigned-clocks = <&gclk 0>;
50 clocks = <&gclk 25>, <&mclk 0x1c 6>;
52 atmel,assigned-clocks = <&gclk 0>;
62 clocks = <&gclk 26>, <&mclk 0x10 8>;
64 atmel,assigned-clocks = <&gclk 0>;
77 clocks = <&gclk 27>, <&mclk 0x10 9>;
79 atmel,assigned-clocks = <&gclk 0>;
Dsam3x.dtsi59 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
69 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
78 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
102 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
111 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
122 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
132 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
148 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
156 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
[all …]
Dsamd5x.dtsi181 clocks = <&gclk 7>, <&mclk 0x14 12>;
183 atmel,assigned-clocks = <&gclk 0>;
192 clocks = <&gclk 8>, <&mclk 0x14 13>;
194 atmel,assigned-clocks = <&gclk 0>;
203 clocks = <&gclk 23>, <&mclk 0x18 9>;
205 atmel,assigned-clocks = <&gclk 0>;
214 clocks = <&gclk 24>, <&mclk 0x18 10>;
216 atmel,assigned-clocks = <&gclk 0>;
225 clocks = <&gclk 34>, <&mclk 0x20 0>;
227 atmel,assigned-clocks = <&gclk 0>;
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2350.dtsi42 clocks {
45 clocks = <&pll_sys>;
54 clocks = <&pll_sys>;
62 clocks = <&pll_sys>;
70 clocks = <&pll_sys>;
78 clocks = <&pll_sys>;
86 clocks = <&xosc>;
94 clocks = <&pll_sys>;
102 clocks = <&pll_usb>;
110 clocks = <&pll_usb>;
[all …]
Drp2040.dtsi46 clocks {
49 clocks = <&pll_sys>;
58 clocks = <&pll_sys>;
66 clocks = <&pll_sys>;
74 clocks = <&pll_sys>;
82 clocks = <&xosc>;
90 clocks = <&pll_sys>;
98 clocks = <&pll_usb>;
106 clocks = <&pll_usb>;
114 clocks = <&pll_usb>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32bg27.dtsi13 clocks {
17 clocks = <&hfxo>;
22 clocks = <&hfrcodpll>;
27 clocks = <&em01grpaclk>;
42 clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_EM01GRPACLK>;
73 clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
110 clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
115 clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
120 clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
125 clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
[all …]
Defr32xg23.dtsi21 clocks {
25 clocks = <&hfxo>;
30 clocks = <&hfrcodpll>;
35 clocks = <&hfrcodpll>;
40 clocks = <&sysclk>;
47 clocks = <&hclk>;
54 clocks = <&pclk>;
61 clocks = <&hclk>;
68 clocks = <&sysclk>;
75 clocks = <&hfrcodpll>;
[all …]
/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f446ze.overlay7 clocks = <&clk_hse>;
14 /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>;
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/
25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
Dnucleo_f411re.overlay7 clocks = <&clk_hse>;
19 clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>;
20 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
21 /* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */
22 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>; */
30 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dsystem_clocks.dtsi10 clocks {
39 clocks = <&clk_iho>;
47 clocks = <&clk_iho>;
55 clocks = <&clk_iho>;
63 clocks = <&clk_imo>;
72 clocks = <&fll0>;
81 clocks = <&fll0>;
90 clocks = <&path_mux2>;
99 clocks = <&path_mux1>;
/Zephyr-latest/dts/arm/nuvoton/
Dm46x.dtsi92 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC
102 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC
112 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC
122 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC
132 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC
142 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC
152 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC
162 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC
172 clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_CLKSEL2_UART8SEL_HIRC
182 clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_CLKSEL2_UART9SEL_HIRC
[all …]
Dm55m1x.dtsi84 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC
94 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC
104 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC
114 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC
124 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC
134 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC
144 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC
154 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC
164 clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC
174 clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay27 /delete-property/ clocks;
32 /delete-property/ clocks;
55 clocks = <&clk_hsi>;
60 clocks = <&pll>;
67 /delete-property/ clocks;
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
80 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi10 clocks {
24 clocks = <&clk_imo>;
32 clocks = <&clk_imo>;
40 clocks = <&clk_imo>;
48 clocks = <&clk_imo>;
56 clocks = <&clk_imo>;
81 clocks = <&fll0>;
90 clocks = <&path_mux1>;
99 clocks = <&path_mux2>;
108 clocks = <&path_mux3>;
[all …]
/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h53 DT_PROP_HAS_IDX(node_id, clocks, idx)
84 DT_PROP_HAS_NAME(node_id, clocks, name)
108 DT_PROP_LEN(node_id, clocks)
137 DT_PHANDLE_BY_IDX(node_id, clocks, idx)
174 DT_PHANDLE_BY_NAME(node_id, clocks, name)
208 DT_PHA_BY_IDX(node_id, clocks, idx, cell)
244 DT_PHA_BY_NAME(node_id, clocks, name, cell)
/Zephyr-latest/dts/arm/nxp/
Dnxp_ke1xf.dtsi152 clocks = <&sosc_clk>;
160 clocks = <&pll>;
167 clocks = <&firc_clk>;
174 clocks = <&core_clk>;
181 clocks = <&core_clk>;
189 clocks = <&firc_clk>;
195 clocks = <&spll_clk>;
202 clocks = <&spll_clk>;
209 clocks = <&sirc_clk>;
216 clocks = <&sirc_clk>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi12 #include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
75 clocks = <&cctl GD32_CLOCK_USART0>;
84 clocks = <&cctl GD32_CLOCK_USART1>;
93 clocks = <&cctl GD32_CLOCK_USART2>;
102 clocks = <&cctl GD32_CLOCK_UART3>;
111 clocks = <&cctl GD32_CLOCK_UART4>;
120 clocks = <&cctl GD32_CLOCK_USART5>;
129 clocks = <&cctl GD32_CLOCK_UART6>;
138 clocks = <&cctl GD32_CLOCK_UART7>;
146 clocks = <&cctl GD32_CLOCK_DAC>;
[all …]
/Zephyr-latest/dts/arm/st/l4/
Dstm32l431.dtsi11 clocks {
28 clocks = <&rcc STM32_CLOCK(AHB2, 3U)>;
36 clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
44 clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
53 clocks = <&rcc STM32_CLOCK(APB1, 22U)>;
65 clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
75 clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
83 clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
92 clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
108 clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi13 #include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
77 clocks = <&cctl GD32_CLOCK_USART0>;
86 clocks = <&cctl GD32_CLOCK_USART1>;
95 clocks = <&cctl GD32_CLOCK_USART2>;
104 clocks = <&cctl GD32_CLOCK_UART3>;
113 clocks = <&cctl GD32_CLOCK_UART4>;
122 clocks = <&cctl GD32_CLOCK_SPI0>;
133 clocks = <&cctl GD32_CLOCK_SPI1>;
144 clocks = <&cctl GD32_CLOCK_SPI2>;
155 clocks = <&cctl GD32_CLOCK_ADC0>;
[all …]

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