1/*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "efr32bg2x.dtsi"
8#include <dt-bindings/clock/silabs/xg27-clock.h>
9#include <mem.h>
10
11/ {
12	clocks {
13		hfxort: hfxort {
14			#clock-cells = <0>;
15			compatible = "fixed-factor-clock";
16			clocks = <&hfxo>;
17		};
18		hfrcodpllrt: hfrcodpllrt {
19			#clock-cells = <0>;
20			compatible = "fixed-factor-clock";
21			clocks = <&hfrcodpll>;
22		};
23		eusart0clk: eusart0clk {
24			#clock-cells = <0>;
25			compatible = "fixed-factor-clock";
26			clocks = <&em01grpaclk>;
27		};
28	};
29
30	soc {
31		clkin0: clkin0@5003c460 {
32			#clock-cells = <0>;
33			compatible = "fixed-clock";
34			reg = <0x5003c460 0x4>;
35			clock-frequency = <DT_FREQ_M(38)>;
36		};
37	};
38};
39
40&cmu {
41	interrupts = <52 0>;
42};
43
44&hfxo {
45	interrupts = <50 0>;
46	interrupt-names = "hfxo";
47};
48
49&msc {
50	flash0: flash@8000000 {
51		compatible = "soc-nv-flash";
52		write-block-size = <4>;
53		erase-block-size = <8192>;
54		reg = <0x08000000 DT_SIZE_K(768)>;
55	};
56};
57
58&sram0 {
59	reg = <0x20000000 DT_SIZE_K(64)>;
60};
61
62&gpio {
63	interrupts = <30 2 31 2>;
64	clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
65};
66
67&i2c0 {
68	interrupts = <32 0>;
69	clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
70};
71
72&i2c1 {
73	interrupts = <33 0>;
74	clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
75};
76
77&usart0 {
78	interrupts = <16 0>, <17 0>;
79	clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
80};
81
82&usart1 {
83	interrupts = <18 0>, <19 0>;
84	clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
85};
86
87&burtc0 {
88	interrupts = <23 0>;
89	clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
90};
91
92&rtcc0 {
93	interrupts = <15 0>;
94	interrupt-names = "rtcc";
95	clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
96};
97
98&adc0 {
99	interrupts = <54 0>;
100	clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
101};
102
103&dcdc {
104	interrupts = <8 0>;
105};
106
107&dma0 {
108	interrupts = <26 0>;
109};
110