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Searched refs:UART1_INTR_SOURCE (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c2-intmux.h28 #define UART1_INTR_SOURCE 18 macro
Desp-esp32c3-intmux.h32 #define UART1_INTR_SOURCE 22 macro
Desp-xtensa-intmux.h45 #define UART1_INTR_SOURCE 35 /* UART1, level */ macro
Desp-esp32c6-intmux.h54 #define UART1_INTR_SOURCE 44 /* interrupt of UART1, level*/ macro
Desp32s3-xtensa-intmux.h37 #define UART1_INTR_SOURCE 28 /* interrupt of UART1, level*/ macro
Desp32s2-xtensa-intmux.h48 #define UART1_INTR_SOURCE 38 /* UART1, level */ macro
/Zephyr-latest/dts/riscv/espressif/esp32c2/
Desp32c2_common.dtsi160 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi243 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/riscv/espressif/esp32c3/
Desp32c3_common.dtsi207 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s2/
Desp32s2_common.dtsi166 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32/
Desp32_common.dtsi226 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
/Zephyr-latest/dts/xtensa/espressif/esp32s3/
Desp32s3_common.dtsi212 interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;