1 /* 2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C3_INTMUX_H_ 9 10 #define WIFI_MAC_INTR_SOURCE 0 11 #define WIFI_MAC_NMI_SOURCE 1 12 #define WIFI_PWR_INTR_SOURCE 2 13 #define WIFI_BB_INTR_SOURCE 3 14 #define BT_MAC_INTR_SOURCE 4 15 #define BT_BB_INTR_SOURCE 5 16 #define BT_BB_NMI_SOURCE 6 17 #define RWBT_INTR_SOURCE 7 18 #define RWBLE_INTR_SOURCE 8 19 #define RWBT_NMI_SOURCE 9 20 #define RWBLE_NMI_SOURCE 10 21 #define I2C_MASTER_SOURCE 11 22 #define SLC0_INTR_SOURCE 12 23 #define SLC1_INTR_SOURCE 13 24 #define APB_CTRL_INTR_SOURCE 14 25 #define UHCI0_INTR_SOURCE 15 26 #define GPIO_INTR_SOURCE 16 27 #define GPIO_NMI_SOURCE 17 28 #define SPI1_INTR_SOURCE 18 29 #define SPI2_INTR_SOURCE 19 30 #define I2S1_INTR_SOURCE 20 31 #define UART0_INTR_SOURCE 21 32 #define UART1_INTR_SOURCE 22 33 #define LEDC_INTR_SOURCE 23 34 #define EFUSE_INTR_SOURCE 24 35 #define TWAI_INTR_SOURCE 25 36 #define USB_INTR_SOURCE 26 37 #define RTC_CORE_INTR_SOURCE 27 38 #define RMT_INTR_SOURCE 28 39 #define I2C_EXT0_INTR_SOURCE 29 40 #define TIMER1_INTR_SOURCE 30 41 #define TIMER2_INTR_SOURCE 31 42 #define TG0_T0_LEVEL_INTR_SOURCE 32 43 #define TG0_WDT_LEVEL_INTR_SOURCE 33 44 #define TG1_T0_LEVEL_INTR_SOURCE 34 45 #define TG1_WDT_LEVEL_INTR_SOURCE 35 46 #define CACHE_IA_INTR_SOURCE 36 47 #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 37 48 #define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 38 49 #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 39 50 #define SPI_MEM_REJECT_CACHE_INTR_SOURCE 40 51 #define ICACHE_PRELOAD0_INTR_SOURCE 41 52 #define ICACHE_SYNC0_INTR_SOURCE 42 53 #define APB_ADC_INTR_SOURCE 43 54 #define DMA_CH0_INTR_SOURCE 44 55 #define DMA_CH1_INTR_SOURCE 45 56 #define DMA_CH2_INTR_SOURCE 46 57 #define RSA_INTR_SOURCE 47 58 #define AES_INTR_SOURCE 48 59 #define SHA_INTR_SOURCE 49 60 #define FROM_CPU_INTR0_SOURCE 50 61 #define FROM_CPU_INTR1_SOURCE 51 62 #define FROM_CPU_INTR2_SOURCE 52 63 #define FROM_CPU_INTR3_SOURCE 53 64 #define ASSIST_DEBUG_INTR_SOURCE 54 65 #define DMA_APBPERI_PMS_INTR_SOURCE 55 66 #define CORE0_IRAM0_PMS_INTR_SOURCE 56 67 #define CORE0_DRAM0_PMS_INTR_SOURCE 57 68 #define CORE0_PIF_PMS_INTR_SOURCE 58 69 #define CORE0_PIF_PMS_SIZE_INTR_SOURCE 59 70 #define BAK_PMS_VIOLATE_INTR_SOURCE 60 71 #define CACHE_CORE0_ACS_INTR_SOURCE 61 72 73 /* RISC-V supports priority values from 1 (lowest) to 15. 74 * As interrupt controller for Xtensa and RISC-V is shared, this is 75 * set to an intermediate and compatible value. 76 */ 77 #define IRQ_DEFAULT_PRIORITY 3 78 79 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ 80 81 #endif 82
