1 /* 2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_XTENSA_INTMUX_H_ 9 10 #define WIFI_MAC_INTR_SOURCE 0 /* WiFi MAC, level */ 11 #define WIFI_MAC_NMI_SOURCE 1 /* WiFi MAC, NMI, use if MAC needs fix in NMI */ 12 #define WIFI_BB_INTR_SOURCE 2 /* WiFi BB, level, we can do some calibration */ 13 #define BT_MAC_INTR_SOURCE 3 /* will be cancelled */ 14 #define BT_BB_INTR_SOURCE 4 /* BB, level */ 15 #define BT_BB_NMI_SOURCE 5 /* BT BB, NMI, use if BB have bug to fix in NMI */ 16 #define RWBT_INTR_SOURCE 6 /* RWBT, level */ 17 #define RWBLE_INTR_SOURCE 7 /* RWBLE, level */ 18 #define RWBT_NMI_SOURCE 8 /* RWBT, NMI, use if RWBT has bug to fix in NMI */ 19 #define RWBLE_NMI_SOURCE 9 /* RWBLE, NMI, use if RWBT has bug to fix in NMI */ 20 #define SLC0_INTR_SOURCE 10 /* SLC0, level */ 21 #define SLC1_INTR_SOURCE 11 /* SLC1, level */ 22 #define UHCI0_INTR_SOURCE 12 /* UHCI0, level */ 23 #define UHCI1_INTR_SOURCE 13 /* UHCI1, level */ 24 #define TG0_T0_LEVEL_INTR_SOURCE 14 /* TIMER_GROUP0, TIMER0, level */ 25 #define TG0_T1_LEVEL_INTR_SOURCE 15 /* TIMER_GROUP0, TIMER1, level */ 26 #define TG0_WDT_LEVEL_INTR_SOURCE 16 /* TIMER_GROUP0, WATCHDOG, level */ 27 #define TG0_LACT_LEVEL_INTR_SOURCE 17 /* TIMER_GROUP0, LACT, level */ 28 #define TG1_T0_LEVEL_INTR_SOURCE 18 /* TIMER_GROUP1, TIMER0, level */ 29 #define TG1_T1_LEVEL_INTR_SOURCE 19 /* TIMER_GROUP1, TIMER1, level */ 30 #define TG1_WDT_LEVEL_INTR_SOURCE 20 /* TIMER_GROUP1, WATCHDOG, level */ 31 #define TG1_LACT_LEVEL_INTR_SOURCE 21 /* TIMER_GROUP1, LACT, level */ 32 #define GPIO_INTR_SOURCE 22 /* interrupt of GPIO, level */ 33 #define GPIO_NMI_SOURCE 23 /* interrupt of GPIO, NMI */ 34 #define FROM_CPU_INTR0_SOURCE 24 /* int0 from a CPU, level */ 35 #define FROM_CPU_INTR1_SOURCE 25 /* int1 from a CPU, level */ 36 #define FROM_CPU_INTR2_SOURCE 26 /* int2 from a CPU, level, for DPORT Access */ 37 #define FROM_CPU_INTR3_SOURCE 27 /* int3 from a CPU, level, for DPORT Access */ 38 #define SPI0_INTR_SOURCE 28 /* SPI0, level, for $ Access, do not use this */ 39 #define SPI1_INTR_SOURCE 29 /* SPI1, level, flash r/w, do not use this */ 40 #define SPI2_INTR_SOURCE 30 /* SPI2, level */ 41 #define SPI3_INTR_SOURCE 31 /* SPI3, level */ 42 #define I2S0_INTR_SOURCE 32 /* I2S0, level */ 43 #define I2S1_INTR_SOURCE 33 /* I2S1, level */ 44 #define UART0_INTR_SOURCE 34 /* UART0, level */ 45 #define UART1_INTR_SOURCE 35 /* UART1, level */ 46 #define UART2_INTR_SOURCE 36 /* UART2, level */ 47 #define SDIO_HOST_INTR_SOURCE 37 /* SD/SDIO/MMC HOST, level */ 48 #define ETH_MAC_INTR_SOURCE 38 /* ethernet mac, level */ 49 #define PWM0_INTR_SOURCE 39 /* PWM0, level, Reserved */ 50 #define PWM1_INTR_SOURCE 40 /* PWM1, level, Reserved */ 51 #define PWM2_INTR_SOURCE 41 /* PWM2, level */ 52 #define PWM3_INTR_SOURCE 42 /* PWM3, level */ 53 #define LEDC_INTR_SOURCE 43 /* LED PWM, level */ 54 #define EFUSE_INTR_SOURCE 44 /* efuse, level, not likely to use */ 55 #define TWAI_INTR_SOURCE 45 /* twai, level */ 56 #define CAN_INTR_SOURCE TWAI_INTR_SOURCE 57 #define RTC_CORE_INTR_SOURCE 46 /* rtc core, level, include rtc watchdog */ 58 #define RMT_INTR_SOURCE 47 /* remote controller, level */ 59 #define PCNT_INTR_SOURCE 48 /* pulse count, level */ 60 #define I2C_EXT0_INTR_SOURCE 49 /* I2C controller1, level */ 61 #define I2C_EXT1_INTR_SOURCE 50 /* I2C controller0, level */ 62 #define RSA_INTR_SOURCE 51 /* RSA accelerator, level */ 63 #define SPI1_DMA_INTR_SOURCE 52 /* SPI1 DMA, for flash r/w, do not use it */ 64 #define SPI2_DMA_INTR_SOURCE 53 /* SPI2 DMA, level */ 65 #define SPI3_DMA_INTR_SOURCE 54 /* interrupt of SPI3 DMA, level */ 66 #define WDT_INTR_SOURCE 55 /* will be cancelled */ 67 #define TIMER1_INTR_SOURCE 56 /* will be cancelled */ 68 #define TIMER2_INTR_SOURCE 57 /* will be cancelled */ 69 #define TG0_T0_EDGE_INTR_SOURCE 58 /* TIMER_GROUP0, TIMER0, EDGE */ 70 #define TG0_T1_EDGE_INTR_SOURCE 59 /* TIMER_GROUP0, TIMER1, EDGE */ 71 #define TG0_WDT_EDGE_INTR_SOURCE 60 /* TIMER_GROUP0, WATCH DOG, EDGE */ 72 #define TG0_LACT_EDGE_INTR_SOURCE 61 /* TIMER_GROUP0, LACT, EDGE */ 73 #define TG1_T0_EDGE_INTR_SOURCE 62 /* TIMER_GROUP1, TIMER0, EDGE */ 74 #define TG1_T1_EDGE_INTR_SOURCE 63 /* TIMER_GROUP1, TIMER1, EDGE */ 75 #define TG1_WDT_EDGE_INTR_SOURCE 64 /* TIMER_GROUP1, WATCHDOG, EDGE */ 76 #define TG1_LACT_EDGE_INTR_SOURCE 65 /* TIMER_GROUP0, LACT, EDGE */ 77 #define MMU_IA_INTR_SOURCE 66 /* MMU Invalid Access, LEVEL */ 78 #define MPU_IA_INTR_SOURCE 67 /* MPU Invalid Access, LEVEL */ 79 #define CACHE_IA_INTR_SOURCE 68 /* Cache Invalid Access, LEVEL */ 80 #define MAX_INTR_SOURCE 69 /* total number of interrupt sources */ 81 82 /* For Xtensa architecture, zero will allocate low/medium 83 * levels of priority (ESP_INTR_FLAG_LOWMED) 84 */ 85 #define IRQ_DEFAULT_PRIORITY 0 86 87 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ 88 89 #endif 90
