1 /* 2 * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_ 8 #define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_ 9 10 #define WIFI_MAC_INTR_SOURCE 0 /* interrupt of WiFi MAC, level*/ 11 #define WIFI_MAC_NMI_SOURCE 1 /* interrupt of WiFi MAC, NMI*/ 12 #define WIFI_PWR_INTR_SOURCE 2 13 #define WIFI_BB_INTR_SOURCE 3 /* interrupt of WiFi BB, level*/ 14 #define BT_MAC_INTR_SOURCE 4 /* will be cancelled*/ 15 #define BT_BB_INTR_SOURCE 5 /* interrupt of BT BB, level*/ 16 #define BT_BB_NMI_SOURCE 6 /* interrupt of BT BB, NMI*/ 17 #define LP_TIMER_INTR_SOURCE 7 18 #define COEX_INTR_SOURCE 8 19 #define BLE_TIMER_INTR_SOURCE 9 20 #define BLE_SEC_INTR_SOURCE 10 21 #define I2C_MASTER_SOURCE 11 /* interrupt of I2C Master, level*/ 22 #define ZB_MAC_SOURCE 12 23 #define PMU_INTR_SOURCE 13 24 #define EFUSE_INTR_SOURCE 14 /* interrupt of efuse, level, not likely to use*/ 25 #define LP_RTC_TIMER_INTR_SOURCE 15 26 #define LP_UART_INTR_SOURCE 16 27 #define LP_I2C_INTR_SOURCE 17 28 #define LP_WDT_INTR_SOURCE 18 29 #define LP_PERI_TIMEOUT_INTR_SOURCE 19 30 #define LP_APM_M0_INTR_SOURCE 20 31 #define LP_APM_M1_INTR_SOURCE 21 32 #define FROM_CPU_INTR0_SOURCE 22 /* interrupt0 generated from a CPU, level*/ 33 #define FROM_CPU_INTR1_SOURCE 23 /* interrupt1 generated from a CPU, level*/ 34 #define FROM_CPU_INTR2_SOURCE 24 /* interrupt2 generated from a CPU, level*/ 35 #define FROM_CPU_INTR3_SOURCE 25 /* interrupt3 generated from a CPU, level*/ 36 #define ASSIST_DEBUG_INTR_SOURCE 26 /* interrupt of Assist debug module, LEVEL*/ 37 #define TRACE_INTR_SOURCE 27 38 #define CACHE_INTR_SOURCE 28 39 #define CPU_PERI_TIMEOUT_INTR_SOURCE 29 40 #define GPIO_INTR_SOURCE 30 /* interrupt of GPIO, level*/ 41 #define GPIO_NMI_SOURCE 31 /* interrupt of GPIO, NMI*/ 42 #define PAU_INTR_SOURCE 32 43 #define HP_PERI_TIMEOUT_INTR_SOURCE 33 44 #define MODEM_PERI_TIMEOUT_INTR_SOURCE 34 45 #define HP_APM_M0_INTR_SOURCE 35 46 #define HP_APM_M1_INTR_SOURCE 36 47 #define HP_APM_M2_INTR_SOURCE 37 48 #define HP_APM_M3_INTR_SOURCE 38 49 #define LP_APM0_INTR_SOURCE 39 50 #define MSPI_INTR_SOURCE 40 51 #define I2S1_INTR_SOURCE 41 /* interrupt of I2S1, level*/ 52 #define UHCI0_INTR_SOURCE 42 /* interrupt of UHCI0, level*/ 53 #define UART0_INTR_SOURCE 43 /* interrupt of UART0, level*/ 54 #define UART1_INTR_SOURCE 44 /* interrupt of UART1, level*/ 55 #define LEDC_INTR_SOURCE 45 /* interrupt of LED PWM, level*/ 56 #define TWAI0_INTR_SOURCE 46 /* interrupt of can0, level*/ 57 #define TWAI1_INTR_SOURCE 47 /* interrupt of can1, level*/ 58 #define USB_SERIAL_JTAG_INTR_SOURCE 48 /* interrupt of USB, level*/ 59 #define RMT_INTR_SOURCE 49 /* interrupt of remote controller, level*/ 60 #define I2C_EXT0_INTR_SOURCE 50 /* interrupt of I2C controller1, level*/ 61 #define TG0_T0_LEVEL_INTR_SOURCE 51 /* interrupt of TIMER_GROUP0, TIMER0, level*/ 62 #define TG0_T1_LEVEL_INTR_SOURCE 52 /* interrupt of TIMER_GROUP0, TIMER1, level*/ 63 #define TG0_WDT_LEVEL_INTR_SOURCE 53 /* interrupt of TIMER_GROUP0, WATCH DOG, level*/ 64 #define TG1_T0_LEVEL_INTR_SOURCE 54 /* interrupt of TIMER_GROUP1, TIMER0, level*/ 65 #define TG1_T1_LEVEL_INTR_SOURCE 55 /* interrupt of TIMER_GROUP1, TIMER1, level*/ 66 #define TG1_WDT_LEVEL_INTR_SOURCE 56 /* interrupt of TIMER_GROUP1, WATCHDOG, level*/ 67 #define SYSTIMER_TARGET0_EDGE_INTR_SOURCE 57 /* interrupt of system timer 0, EDGE*/ 68 #define SYSTIMER_TARGET1_EDGE_INTR_SOURCE 58 /* interrupt of system timer 1, EDGE*/ 69 #define SYSTIMER_TARGET2_EDGE_INTR_SOURCE 59 /* interrupt of system timer 2, EDGE*/ 70 #define APB_ADC_INTR_SOURCE 60 /* interrupt of APB ADC, LEVEL*/ 71 #define MCPWM0_INTR_SOURCE 61 /* interrupt of MCPWM0, LEVEL*/ 72 #define PCNT_INTR_SOURCE 62 73 #define PARL_IO_INTR_SOURCE 63 74 #define SLC0_INTR_SOURCE 64 75 #define SLC_INTR_SOURCE 65 76 #define DMA_IN_CH0_INTR_SOURCE 66 /* interrupt of general DMA IN channel 0, LEVEL*/ 77 #define DMA_IN_CH1_INTR_SOURCE 67 /* interrupt of general DMA IN channel 1, LEVEL*/ 78 #define DMA_IN_CH2_INTR_SOURCE 68 /* interrupt of general DMA IN channel 2, LEVEL*/ 79 #define DMA_OUT_CH0_INTR_SOURCE 69 /* interrupt of general DMA OUT channel 0, LEVEL*/ 80 #define DMA_OUT_CH1_INTR_SOURCE 70 /* interrupt of general DMA OUT channel 1, LEVEL*/ 81 #define DMA_OUT_CH2_INTR_SOURCE 71 /* interrupt of general DMA OUT channel 2, LEVEL*/ 82 #define GSPI2_INTR_SOURCE 72 83 #define AES_INTR_SOURCE 73 /* interrupt of AES accelerator, level*/ 84 #define SHA_INTR_SOURCE 74 /* interrupt of SHA accelerator, level*/ 85 #define RSA_INTR_SOURCE 75 /* interrupt of RSA accelerator, level*/ 86 #define ECC_INTR_SOURCE 76 /* interrupt of ECC accelerator, level*/ 87 #define MAX_INTR_SOURCE 77 88 89 /* RISC-V supports priority values from 1 (lowest) to 15. 90 * As interrupt controller for Xtensa and RISC-V is shared, this is 91 * set to an intermediate and compatible value. 92 */ 93 #define IRQ_DEFAULT_PRIORITY 3 94 95 #define ESP_INTR_FLAG_SHARED (1<<8) /* Interrupt can be shared between ISRs */ 96 97 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ESP32C6_INTMUX_H_ */ 98
